From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH v3] drm/i915: Added write-enable pte bit support Date: Wed, 14 May 2014 10:14:40 +0200 Message-ID: <20140514081440.GA8790@phenom.ffwll.local> References: <1392108543-31552-1-git-send-email-akash.goel@intel.com> <20140513150524.4050090c@jbarnes-desktop> <20140513223034.GX3908@phenom.ffwll.local> <20140513154312.45ad15ec@jbarnes-desktop> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ee0-f46.google.com (mail-ee0-f46.google.com [74.125.83.46]) by gabe.freedesktop.org (Postfix) with ESMTP id 617CB6EC14 for ; Wed, 14 May 2014 01:15:21 -0700 (PDT) Received: by mail-ee0-f46.google.com with SMTP id t10so1062190eei.19 for ; Wed, 14 May 2014 01:15:20 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140513154312.45ad15ec@jbarnes-desktop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Jesse Barnes Cc: akash.goel@intel.com, intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, May 13, 2014 at 03:43:12PM -0700, Jesse Barnes wrote: > On Wed, 14 May 2014 00:30:34 +0200 > Daniel Vetter wrote: > > > On Tue, May 13, 2014 at 03:05:24PM -0700, Jesse Barnes wrote: > > > On Tue, 11 Feb 2014 14:19:03 +0530 > > > akash.goel@intel.com wrote: > > > > > > > @@ -810,6 +815,7 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, > > > > pt_vaddr[act_pte] = > > > > vm->pte_encode(sg_page_iter_dma_address(&sg_iter), > > > > cache_level, true); > > > > + > > > > if (++act_pte == I915_PPGTT_PT_ENTRIES) { > > > > kunmap_atomic(pt_vaddr); > > > > pt_vaddr = NULL; > > > > > > Some extra whitespace here. > > > > > > Otherwise: > > > Reviewed-by: Jesse Barnes > > > > Hm, looking at the patch again encoding this into the cache_level enum is > > fraught with fun. And due to IS_VLV aliasing chv this will blow up on chv > > very likely. My old idea was to eventually add a pte_flags param all over > > for this stuff with additional bits. > > That works too; and yeah CHV is all different here isn't it. But won't > it go through the gen8 paths anyway? Yes, but we have a switch on the cache_level in the gen8 pte encode function. Since the bit31 gets or'ed in for VLV, it'll hit also chv and wreak havoc in that specific switch - we'll hit the default case when we don't expect to. cache_level = functional behaviour relevant for the kernel's clflushing code > Ack on the cache_level abuse though; it's an implementation detail that > should be changed if/when this is properly exposed to userspace (or > maybe we shouldn't bother and just use CHV/BDW stuff going forward, > supporting a proper mprotect ioctl). Not talking about exposing to userspace, but adding pte_flags to the low-level platform pte encode functions to prevent the above bugs. I'm ok with keeping obj->gt_ro. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch