From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 00/10] Enable RC6/Turbo on CHV
Date: Thu, 15 May 2014 23:22:41 +0200
Message-ID: <20140515212241.GC8790@phenom.ffwll.local>
References: <1399294059-20748-1-git-send-email-deepak.s@linux.intel.com>
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On Mon, May 05, 2014 at 06:17:29PM +0530, deepak.s@linux.intel.com wrote:
> From: Deepak S <deepak.s@linux.intel.com>
> =

> Squashed some of the patches and created a new patch series. Addressed re=
view comments on most of the patches.
> =

> Ben Widawsky (1):
>   drm/i915/bdw: Implement a basic PM interrupt handler
> =

> Deepak S (7):
>   drm/i915: Enable PM Interrupts target via Display Interface.
>   drm/i915/chv: Enable Render Standby (RC6) for Cherryview
>   drm/i915/chv: Added CHV specific register read and write
>   drm/i915/chv: Streamline CHV forcewake stuff
>   drm/i915/chv: Enable RPS (Turbo) for Cherryview
>   drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating
>   drm/i915/chv: Freq(opcode) request for CHV.
> =

> Ville Syrj=E4l=E4 (2):
>   drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0
>   drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV

Just for coordination: I've just pulled in the bdw-only series from Mika,
so I guess you need to rebase the chv patches on top of drm-intel-nightly.
I think -nightly has now enough of the chv stuff merged that this should
work out. Otherwise I need to beat up the reviewers to not slack off this
much :(
-Daniel
-- =

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch