From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 2/5] drm/i915/bdw: Implement a basic PM interrupt handler Date: Fri, 16 May 2014 11:09:35 +0200 Message-ID: <20140516090935.GE8790@phenom.ffwll.local> References: <1400176691-5731-1-git-send-email-mika.kuoppala@intel.com> <1400176691-5731-2-git-send-email-mika.kuoppala@intel.com> <411E5DC12A51ED4CB1159E14310E532B9D8A72C3@FMSMSX119.amr.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ee0-f50.google.com (mail-ee0-f50.google.com [74.125.83.50]) by gabe.freedesktop.org (Postfix) with ESMTP id 29B606E285 for ; Fri, 16 May 2014 02:09:40 -0700 (PDT) Received: by mail-ee0-f50.google.com with SMTP id e51so1321275eek.37 for ; Fri, 16 May 2014 02:09:39 -0700 (PDT) Content-Disposition: inline In-Reply-To: <411E5DC12A51ED4CB1159E14310E532B9D8A72C3@FMSMSX119.amr.corp.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "O'Rourke, Tom" Cc: "intel-gfx@lists.freedesktop.org" , "Widawsky, Benjamin" List-Id: intel-gfx@lists.freedesktop.org On Fri, May 16, 2014 at 01:38:18AM +0000, O'Rourke, Tom wrote: > >+static void gen8_disable_rps_interrupts(struct drm_device *dev) { > >+ struct drm_i915_private *dev_priv = dev->dev_private; > >+ > >+ I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); > > [TOR:] Please note that for Broadwell, bit 31 in GEN6_PMINTRMSK is not an interrupt disable bit. > In "drm/i915: Enable PM Interrupts target via Display Interface." this bit is defined as: > +#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) > > Writing this bit here could have unintended consequences. Hm, we seem to unconditionally set this bit on gen8 anyway. Still harmful? Mika, Ville? -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch