From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH 2/2] drm/i915: vlv/chv: fix DSI sideband register accessing Date: Mon, 19 May 2014 08:33:16 -0700 Message-ID: <20140519083316.2b9a4cb8@jbarnes-desktop> References: <1400488878-23130-1-git-send-email-imre.deak@intel.com> <1400488878-23130-2-git-send-email-imre.deak@intel.com> <20140519080111.27f6cd65@jbarnes-desktop> <1400512218.1438.13.camel@intelbox> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from gproxy5-pub.mail.unifiedlayer.com (gproxy5-pub.mail.unifiedlayer.com [67.222.38.55]) by gabe.freedesktop.org (Postfix) with SMTP id 53D946E564 for ; Mon, 19 May 2014 08:33:21 -0700 (PDT) In-Reply-To: <1400512218.1438.13.camel@intelbox> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: imre.deak@intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, 19 May 2014 18:10:18 +0300 Imre Deak wrote: > On Mon, 2014-05-19 at 08:01 -0700, Jesse Barnes wrote: > > On Mon, 19 May 2014 11:41:18 +0300 > > Imre Deak wrote: > > > > > So far we used the wrong opcodes to access the DSI registers, so the > > > register writes during DSI programming didn't actually succeed and left > > > the registers unchanged. This wasn't a problem for the initial modeset, > > > where the BIOS-programmed values happened to work, but after resuming > > > from s0ix these registers are reset and failing to program them results > > > in a blank screen. > > > > > > Signed-off-by: Imre Deak > > > --- > > > drivers/gpu/drm/i915/intel_sideband.c | 4 ++-- > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c > > > index f3909d5..01d841e 100644 > > > --- a/drivers/gpu/drm/i915/intel_sideband.c > > > +++ b/drivers/gpu/drm/i915/intel_sideband.c > > > @@ -270,13 +270,13 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, > > > u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg) > > > { > > > u32 val = 0; > > > - vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MRD_NP, > > > + vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP, > > > reg, &val); > > > return val; > > > } > > > > > > void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val) > > > { > > > - vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MWR_NP, > > > + vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP, > > > reg, &val); > > > } > > > > Nice find... is this documented somewhere so we can put a reference > > in? Or is it in the Punit HAS somewhere already and we just missed it? > > I found it in the VLV2_SidebandMsg_HAS, there is already a comment in > this file with a reference to it. Cool, this one has my Reviewed-by: Jesse Barnes then too. -- Jesse Barnes, Intel Open Source Technology Center