Re: [PATCH 3/6] drm/i915: Fix ILK GPU reset domain bits

From: Jesse Barnes <jbarnes@virtuousgeek.org>
To: ville.syrjala@linux.intel.com
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/6] drm/i915: Fix ILK GPU reset domain bits
Date: Mon, 19 May 2014 09:32:57 -0700	[thread overview]
Message-ID: <20140519093257.33c7d2cb@jbarnes-desktop> (raw)
In-Reply-To: <1400516607-25840-4-git-send-email-ville.syrjala@linux.intel.com>

On Mon, 19 May 2014 19:23:24 +0300
ville.syrjala@linux.intel.com wrote:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We're using the reset domains bits for g4x on ilk. But on ilk those bits
> actually shifted by one bit. Fix it up so that we use the correct bits.
> 
> We were actually always writing 0x2 to the reset domain bits, which
> is a reserved value. In practice it looks like the hardware ignores that
> value since nothing happens if I write that value when there's a 3D
> workload running. Writing the _correct_ render domain value actually
> makes the GPU stop.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h     |  8 +++++++-
>  drivers/gpu/drm/i915/intel_uncore.c | 12 ++++++------
>  2 files changed, 13 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ac90786..6522af4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -79,13 +79,19 @@
>  
>  /* Graphics reset regs */
>  #define I965_GDRST 0xc0 /* PCI config register */
> -#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
>  #define  GRDOM_FULL	(0<<2)
>  #define  GRDOM_RENDER	(1<<2)
>  #define  GRDOM_MEDIA	(3<<2)
>  #define  GRDOM_MASK	(3<<2)
>  #define  GRDOM_RESET_ENABLE (1<<0)
>  
> +#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
> +#define  ILK_GRDOM_FULL		(0<<1)
> +#define  ILK_GRDOM_RENDER	(1<<1)
> +#define  ILK_GRDOM_MEDIA	(3<<1)
> +#define  ILK_GRDOM_MASK		(3<<1)
> +#define  ILK_GRDOM_RESET_ENABLE (1<<0)
> +
>  #define GEN6_MBCUNIT_SNPCR	0x900c /* for LLC config */
>  #define   GEN6_MBC_SNPCR_SHIFT	21
>  #define   GEN6_MBC_SNPCR_MASK	(3<<21)
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index d79db88..008d30b 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -997,20 +997,20 @@ static int ironlake_do_reset(struct drm_device *dev)
>  	int ret;
>  
>  	gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
> -	gdrst &= ~GRDOM_MASK;
> +	gdrst &= ~ILK_GRDOM_MASK;
>  	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
> -		   gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
> +		   gdrst | ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
>  	ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
> -			GRDOM_RESET_ENABLE) == 0, 500);
> +			ILK_GRDOM_RESET_ENABLE) == 0, 500);
>  	if (ret)
>  		return ret;
>  
>  	gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
> -	gdrst &= ~GRDOM_MASK;
> +	gdrst &= ~ILK_GRDOM_MASK;
>  	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
> -		   gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
> +		   gdrst | ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
>  	return wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
> -			 GRDOM_RESET_ENABLE) == 0, 500);
> +			 ILK_GRDOM_RESET_ENABLE) == 0, 500);
>  }
>  
>  static int gen6_do_reset(struct drm_device *dev)

Can't find docs, but if you tested that wins anyway.

Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center
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