From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915: HWS must be in the mappable region for g33 Date: Mon, 19 May 2014 13:17:20 +0300 Message-ID: <20140519101720.GX27580@intel.com> References: <1400482571-25350-1-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id E059D6E413 for ; Mon, 19 May 2014 03:17:24 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1400482571-25350-1-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, May 19, 2014 at 07:56:11AM +0100, Chris Wilson wrote: > This also appears to be true (but not documented as so) for gen4 and > gen5. To generalise we force it into the low mappable region for all > non-LLC platforms. If we locate the HWS at the top of the GTT the > machine will hard hang during boot (fails on pnv, gm45, ilk and byt, > but works on snb, ivb, hsw). I take it this is the documented part? "[DevBLB] Only: Format =3D Bits 28:12 of graphics memory address (bits 31:29 MBZ)." > = > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > = > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9= 15/intel_ringbuffer.c > index cb6d510245b5..9576b8f57150 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -1362,6 +1362,7 @@ static int init_status_page(struct intel_ring_buffe= r *ring) > struct drm_i915_gem_object *obj; > = > if ((obj =3D ring->status_page.obj) =3D=3D NULL) { > + unsigned flags; > int ret; > = > obj =3D i915_gem_alloc_object(ring->dev, 4096); > @@ -1374,7 +1375,10 @@ static int init_status_page(struct intel_ring_buff= er *ring) > if (ret) > goto err_unref; > = > - ret =3D i915_gem_obj_ggtt_pin(obj, 4096, 0); > + flags =3D 0; > + if (!HAS_LLC(ring->dev)) > + flags |=3D PIN_MAPPABLE; Maybe there should be a comment why we need PIN_MAPPABLE even though we never map it? > + ret =3D i915_gem_obj_ggtt_pin(obj, 0, flags); Why the alignment change? Well, I guess it'll end up 4k aligned anyway since it's not tiled. > if (ret) { > err_unref: > drm_gem_object_unreference(&obj->base); > -- = > 2.0.0.rc2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC