From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: FW: [PATCH v8 3/9] drm/i915: Make sprite updates atomic Date: Mon, 19 May 2014 13:49:55 +0300 Message-ID: <20140519104955.GZ27580@intel.com> References: <1398767752-619-1-git-send-email-ville.syrjala@linux.intel.com> <1398767752-619-4-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 4C0656E6E3 for ; Mon, 19 May 2014 03:49:59 -0700 (PDT) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Arun Murthy Cc: intel-gfx List-Id: intel-gfx@lists.freedesktop.org On Mon, May 19, 2014 at 04:08:09PM +0530, Arun Murthy wrote: > > Add a mechanism by which we can evade the leading edge of vblank. This > > guarantees that no two sprite register writes will straddle on either > > side of the vblank start, and that means all the writes will be latched > > together in one atomic operation. > = > = > Here only one sprite update followed by the primary enable/disable can be > achieved atomically. But I feel update of all planes are to be considered= , i.e > update of planes per pipe basis to achieve atomicity. That's the final goal. This patch introduces the mechanism by which we can eventually implement the full atomic update. -- = Ville Syrj=E4l=E4 Intel OTC