From: Daniel Vetter <daniel@ffwll.ch>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/i915: vlv/chv: fix DSI sideband register accessing
Date: Mon, 19 May 2014 17:50:45 +0200 [thread overview]
Message-ID: <20140519155045.GU8790@phenom.ffwll.local> (raw)
In-Reply-To: <20140519083316.2b9a4cb8@jbarnes-desktop>
On Mon, May 19, 2014 at 08:33:16AM -0700, Jesse Barnes wrote:
> On Mon, 19 May 2014 18:10:18 +0300
> Imre Deak <imre.deak@intel.com> wrote:
>
> > On Mon, 2014-05-19 at 08:01 -0700, Jesse Barnes wrote:
> > > On Mon, 19 May 2014 11:41:18 +0300
> > > Imre Deak <imre.deak@intel.com> wrote:
> > >
> > > > So far we used the wrong opcodes to access the DSI registers, so the
> > > > register writes during DSI programming didn't actually succeed and left
> > > > the registers unchanged. This wasn't a problem for the initial modeset,
> > > > where the BIOS-programmed values happened to work, but after resuming
> > > > from s0ix these registers are reset and failing to program them results
> > > > in a blank screen.
> > > >
> > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/intel_sideband.c | 4 ++--
> > > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> > > > index f3909d5..01d841e 100644
> > > > --- a/drivers/gpu/drm/i915/intel_sideband.c
> > > > +++ b/drivers/gpu/drm/i915/intel_sideband.c
> > > > @@ -270,13 +270,13 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
> > > > u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
> > > > {
> > > > u32 val = 0;
> > > > - vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MRD_NP,
> > > > + vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
> > > > reg, &val);
> > > > return val;
> > > > }
> > > >
> > > > void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> > > > {
> > > > - vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_MWR_NP,
> > > > + vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
> > > > reg, &val);
> > > > }
> > >
> > > Nice find... is this documented somewhere so we can put a reference
> > > in? Or is it in the Punit HAS somewhere already and we just missed it?
> >
> > I found it in the VLV2_SidebandMsg_HAS, there is already a comment in
> > this file with a reference to it.
>
> Cool, this one has my
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> then too.
Both patches merged, thanks.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
next prev parent reply other threads:[~2014-05-19 15:50 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-19 8:41 [PATCH 1/2] drm/i915: rename IOSF sideband opcodes according to the spec Imre Deak
2014-05-19 8:41 ` [PATCH 2/2] drm/i915: vlv/chv: fix DSI sideband register accessing Imre Deak
2014-05-19 15:01 ` Jesse Barnes
2014-05-19 15:10 ` Imre Deak
2014-05-19 15:33 ` Jesse Barnes
2014-05-19 15:50 ` Daniel Vetter [this message]
2014-05-26 12:52 ` Jani Nikula
2014-06-02 13:39 ` Kumar, Shobhit
2014-05-19 15:00 ` [PATCH 1/2] drm/i915: rename IOSF sideband opcodes according to the spec Jesse Barnes
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20140519155045.GU8790@phenom.ffwll.local \
--to=daniel@ffwll.ch \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jbarnes@virtuousgeek.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox