From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/6] drm/i915: Fix ILK reset wait
Date: Tue, 20 May 2014 11:18:44 +0300 [thread overview]
Message-ID: <20140520081844.GD27580@intel.com> (raw)
In-Reply-To: <20140520080127.GC8790@phenom.ffwll.local>
On Tue, May 20, 2014 at 10:01:27AM +0200, Daniel Vetter wrote:
> On Mon, May 19, 2014 at 09:30:25AM -0700, Jesse Barnes wrote:
> > On Mon, 19 May 2014 19:23:23 +0300
> > ville.syrjala@linux.intel.com wrote:
> >
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > We should be waiting for the reset bit to clear, not remain set.
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_uncore.c | 6 ++++--
> > > 1 file changed, 4 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> > > index 0e333f2..d79db88 100644
> > > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > > @@ -1000,7 +1000,8 @@ static int ironlake_do_reset(struct drm_device *dev)
> > > gdrst &= ~GRDOM_MASK;
> > > I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
> > > gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
> > > - ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
> > > + ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
> > > + GRDOM_RESET_ENABLE) == 0, 500);
> > > if (ret)
> > > return ret;
> > >
> > > @@ -1008,7 +1009,8 @@ static int ironlake_do_reset(struct drm_device *dev)
> > > gdrst &= ~GRDOM_MASK;
> > > I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
> > > gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
> > > - return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
> > > + return wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
> > > + GRDOM_RESET_ENABLE) == 0, 500);
> > > }
> > >
> > > static int gen6_do_reset(struct drm_device *dev)
> >
> > Arg, I lost the docs on this, but it matches what I remember.
> >
> > Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>
> Was this tested on an ilk? I remember writing a similar patch and I didn't
> apply it due to conflict with reality.
Yes. My ILK seems happy now. Maybe your ILK barfed on it due to
specifying invalid reset domains (fixed in 3/6)?
--
Ville Syrjälä
Intel OTC
next prev parent reply other threads:[~2014-05-20 8:18 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-19 16:23 [PATCH 0/6] drm/i915: g4x/ilk reset fixes ville.syrjala
2014-05-19 16:23 ` [PATCH 1/6] drm/i915: Drop bogus comments about display reset ville.syrjala
2014-05-19 16:29 ` Jesse Barnes
2014-05-19 16:23 ` [PATCH 2/6] drm/i915: Fix ILK reset wait ville.syrjala
2014-05-19 16:30 ` Jesse Barnes
2014-05-20 8:01 ` Daniel Vetter
2014-05-20 8:18 ` Ville Syrjälä [this message]
2014-05-20 8:43 ` Daniel Vetter
2014-05-19 16:23 ` [PATCH 3/6] drm/i915: Fix ILK GPU reset domain bits ville.syrjala
2014-05-19 16:32 ` Jesse Barnes
2014-05-19 16:23 ` [PATCH 4/6] drm/i915: Kill RMW from ILK reset code ville.syrjala
2014-05-20 18:37 ` Jesse Barnes
2014-05-19 16:23 ` [PATCH 5/6] drm/i915: Clear GDSR after reset on ILK ville.syrjala
2014-05-20 18:38 ` Jesse Barnes
2014-05-19 16:23 ` [PATCH 6/6] drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elk ville.syrjala
2014-05-20 18:46 ` Jesse Barnes
2014-05-22 14:35 ` Daniel Vetter
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