From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 2/6] drm/i915: Fix ILK reset wait
Date: Tue, 20 May 2014 11:18:44 +0300
Message-ID: <20140520081844.GD27580@intel.com>
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To: Daniel Vetter <daniel@ffwll.ch>
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On Tue, May 20, 2014 at 10:01:27AM +0200, Daniel Vetter wrote:
> On Mon, May 19, 2014 at 09:30:25AM -0700, Jesse Barnes wrote:
> > On Mon, 19 May 2014 19:23:23 +0300
> > ville.syrjala@linux.intel.com wrote:
> > =

> > > From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > > =

> > > We should be waiting for the reset bit to clear, not remain set.
> > > =

> > > Signed-off-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_uncore.c | 6 ++++--
> > >  1 file changed, 4 insertions(+), 2 deletions(-)
> > > =

> > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i9=
15/intel_uncore.c
> > > index 0e333f2..d79db88 100644
> > > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > > @@ -1000,7 +1000,8 @@ static int ironlake_do_reset(struct drm_device =
*dev)
> > >  	gdrst &=3D ~GRDOM_MASK;
> > >  	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
> > >  		   gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
> > > -	ret =3D wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 50=
0);
> > > +	ret =3D wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
> > > +			GRDOM_RESET_ENABLE) =3D=3D 0, 500);
> > >  	if (ret)
> > >  		return ret;
> > >  =

> > > @@ -1008,7 +1009,8 @@ static int ironlake_do_reset(struct drm_device =
*dev)
> > >  	gdrst &=3D ~GRDOM_MASK;
> > >  	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
> > >  		   gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
> > > -	return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500=
);
> > > +	return wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
> > > +			 GRDOM_RESET_ENABLE) =3D=3D 0, 500);
> > >  }
> > >  =

> > >  static int gen6_do_reset(struct drm_device *dev)
> > =

> > Arg, I lost the docs on this, but it matches what I remember.
> > =

> > Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> =

> Was this tested on an ilk? I remember writing a similar patch and I didn't
> apply it due to conflict with reality.

Yes. My ILK seems happy now. Maybe your ILK barfed on it due to
specifying invalid reset domains (fixed in 3/6)?

-- =

Ville Syrj=E4l=E4
Intel OTC