From mboxrd@z Thu Jan 1 00:00:00 1970 From: Damien Lespiau Subject: Re: [PATCH 38/66] drm/i915: s/ironlake_/intel_ for the enable_share_dpll function Date: Tue, 20 May 2014 11:29:54 +0100 Message-ID: <20140520102954.GC12931@strange.amr.corp.intel.com> References: <1398376542-27825-1-git-send-email-daniel.vetter@ffwll.ch> <1398376542-27825-39-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id F0DE76E8A9 for ; Tue, 20 May 2014 03:29:56 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1398376542-27825-39-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Daniel Vetter Cc: Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Thu, Apr 24, 2014 at 11:55:14PM +0200, Daniel Vetter wrote: > Besides the fairly useless BUG_ON the logic is completely generic > and cane be used on any platform what wants to reuse the shared > dpll support code. > > Signed-off-by: Daniel Vetter Reviewed-by: Damien Lespiau -- Damien > --- > drivers/gpu/drm/i915/intel_display.c | 8 +++----- > 1 file changed, 3 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 96bab640399f..1513d9fceebe 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1568,21 +1568,19 @@ static void intel_prepare_shared_dpll(struct intel_crtc *crtc) > } > > /** > - * ironlake_enable_shared_dpll - enable PCH PLL > + * intel_enable_shared_dpll - enable PCH PLL > * @dev_priv: i915 private structure > * @pipe: pipe PLL to enable > * > * The PCH PLL needs to be enabled before the PCH transcoder, since it > * drives the transcoder clock. > */ > -static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) > +static void intel_enable_shared_dpll(struct intel_crtc *crtc) > { > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); > > - /* PCH PLLs only available on ILK, SNB and IVB */ > - BUG_ON(INTEL_INFO(dev)->gen < 5); > if (WARN_ON(pll == NULL)) > return; > > @@ -3328,7 +3326,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) > * Note that enable_shared_dpll tries to do the right thing, but > * get_shared_dpll unconditionally resets the pll - we need that to have > * the right LVDS enable sequence. */ > - ironlake_enable_shared_dpll(intel_crtc); > + intel_enable_shared_dpll(intel_crtc); > > /* set transcoder timing, panel must allow it */ > assert_panel_unlocked(dev_priv, pipe); > -- > 1.8.1.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx