Re: [PATCH 56/66] drm/i915: Move ddi_pll_sel into the pipe config

[Damien Lespiau <damien.lespiau@intel.com>]

On Thu, Apr 24, 2014 at 11:55:32PM +0200, Daniel Vetter wrote:
> Just boring sed job for preparation.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

We want want a ddi structure to gather all the DDI config fields later
down the road.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/intel_crt.c |  4 ++--
>  drivers/gpu/drm/i915/intel_ddi.c | 30 +++++++++++++++---------------
>  drivers/gpu/drm/i915/intel_drv.h |  5 +++--
>  3 files changed, 20 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index c4b1b1f82d01..beffae116f05 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -186,8 +186,8 @@ static void hsw_fdi_link_train(struct drm_crtc *crtc)
>  	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
>  
>  	/* Configure Port Clock Select */
> -	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
> -	WARN_ON(intel_crtc->ddi_pll_sel != PORT_CLK_SEL_SPLL);
> +	I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel);
> +	WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL);
>  
>  	/* Start the training iterating through available voltages and emphasis,
>  	 * testing each value twice. */
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 534cdb42e788..2adcc917806e 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -262,7 +262,7 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	uint32_t val;
>  
> -	switch (intel_crtc->ddi_pll_sel) {
> +	switch (intel_crtc->config.ddi_pll_sel) {
>  	case PORT_CLK_SEL_WRPLL1:
>  		plls->wrpll1_refcount--;
>  		if (plls->wrpll1_refcount == 0) {
> @@ -288,7 +288,7 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
>  	WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
>  	WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
>  
> -	intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
> +	intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
>  }
>  
>  #define LC_FREQ 2700
> @@ -623,13 +623,13 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
>  
>  		switch (intel_dp->link_bw) {
>  		case DP_LINK_BW_1_62:
> -			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
> +			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
>  			break;
>  		case DP_LINK_BW_2_7:
> -			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
> +			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
>  			break;
>  		case DP_LINK_BW_5_4:
> -			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
> +			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
>  			break;
>  		default:
>  			DRM_ERROR("Link bandwidth %d unsupported\n",
> @@ -673,16 +673,16 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
>  
>  		if (reg == WRPLL_CTL1) {
>  			plls->wrpll1_refcount++;
> -			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
> +			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
>  		} else {
>  			plls->wrpll2_refcount++;
> -			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
> +			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
>  		}
>  
>  	} else if (type == INTEL_OUTPUT_ANALOG) {
>  		DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
>  			      pipe_name(pipe));
> -		intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
> +		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_SPLL;
>  	} else {
>  		WARN(1, "Invalid DDI encoder type %d\n", type);
>  		return false;
> @@ -710,10 +710,10 @@ void intel_ddi_pll_enable(struct intel_crtc *crtc)
>  	BUILD_BUG_ON(enable_bit != SPLL_PLL_ENABLE);
>  	BUILD_BUG_ON(enable_bit != WRPLL_PLL_ENABLE);
>  
> -	switch (crtc->ddi_pll_sel) {
> +	switch (crtc->config.ddi_pll_sel) {
>  	case PORT_CLK_SEL_WRPLL1:
>  	case PORT_CLK_SEL_WRPLL2:
> -		if (crtc->ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
> +		if (crtc->config.ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
>  			pll_name = "WRPLL1";
>  			reg = WRPLL_CTL1;
>  			refcount = plls->wrpll1_refcount;
> @@ -1035,14 +1035,14 @@ void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
>  			to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
>  
>  		if (!intel_crtc->active) {
> -			intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
> +			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
>  			continue;
>  		}
>  
> -		intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
> +		intel_crtc->config.ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
>  								 pipe);
>  
> -		switch (intel_crtc->ddi_pll_sel) {
> +		switch (intel_crtc->config.ddi_pll_sel) {
>  		case PORT_CLK_SEL_WRPLL1:
>  			dev_priv->ddi_plls.wrpll1_refcount++;
>  			break;
> @@ -1098,8 +1098,8 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
>  		intel_edp_panel_on(intel_dp);
>  	}
>  
> -	WARN_ON(crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
> -	I915_WRITE(PORT_CLK_SEL(port), crtc->ddi_pll_sel);
> +	WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE);
> +	I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel);
>  
>  	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
>  		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 77414333804a..e1d079fe47ea 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -307,6 +307,9 @@ struct intel_crtc_config {
>  	/* Selected dpll when shared or DPLL_ID_PRIVATE. */
>  	enum intel_dpll_id shared_dpll;
>  
> +	/* PORT_CLK_SEL for DDI ports. */
> +	uint32_t ddi_pll_sel;
> +
>  	/* Actual register state of the dpll, for shared dpll cross-checking. */
>  	struct intel_dpll_hw_state dpll_hw_state;
>  
> @@ -393,8 +396,6 @@ struct intel_crtc {
>  	struct intel_crtc_config *new_config;
>  	bool new_enabled;
>  
> -	uint32_t ddi_pll_sel;
> -
>  	/* reset counter value when the last flip was submitted */
>  	unsigned int reset_counter;
>  
> -- 
> 1.8.1.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx