From mboxrd@z Thu Jan  1 00:00:00 1970
From: Damien Lespiau <damien.lespiau@intel.com>
Subject: Re: [PATCH 58/66] drm/i915: Precompute static
 ddi_pll_sel values in encoders
Date: Tue, 20 May 2014 11:56:28 +0100
Message-ID: <20140520105628.GG12931@strange.amr.corp.intel.com>
References: <1398376542-27825-1-git-send-email-daniel.vetter@ffwll.ch>
 <1398376542-27825-59-git-send-email-daniel.vetter@ffwll.ch>
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To: Daniel Vetter <daniel.vetter@ffwll.ch>
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On Thu, Apr 24, 2014 at 11:55:34PM +0200, Daniel Vetter wrote:
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -272,6 +272,7 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
>  			I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
>  			POSTING_READ(WRPLL_CTL1);
>  		}
> +		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
>  		break;
>  	case PORT_CLK_SEL_WRPLL2:
>  		plls->wrpll2_refcount--;
> @@ -282,13 +283,12 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
>  			I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
>  			POSTING_READ(WRPLL_CTL2);
>  		}
> +		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
>  		break;
>  	}
>  
>  	WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
>  	WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
> -
> -	intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
>  }

Who sets config.ddi_pll_sel to NONE for VGA and DP now?

-- 
Damien