Re: [PATCH 59/66] drm/i915: Basic shared dpll support for WRPLLs

[Damien Lespiau <damien.lespiau@intel.com>]

On Thu, Apr 24, 2014 at 11:55:35PM +0200, Daniel Vetter wrote:
> Just filing in names and ids, but not yet officially registering them
> so that the hw state cross checker doesn't completely freak out about
> them. Still since we do already read out and cross check
> config->shared_dpll the basics are now there to flesh out the wrpll
> shared dpll implementation.
> 
> The idea is now to roll out all the callbacks step-by-step and then at
> the end switch to the shared dpll framework. This way hw and sw
> changes are clearly separated.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

With the consts added:

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  6 ++++--
>  drivers/gpu/drm/i915/intel_ddi.c     | 17 +++++++++++++++++
>  drivers/gpu/drm/i915/intel_display.c | 21 +++++++++++++--------
>  3 files changed, 34 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b6eac92e0a22..babeb7e92ee4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -176,8 +176,10 @@ struct drm_i915_private;
>  enum intel_dpll_id {
>  	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
>  	/* real shared dpll ids must be >= 0 */
> -	DPLL_ID_PCH_PLL_A,
> -	DPLL_ID_PCH_PLL_B,
> +	DPLL_ID_PCH_PLL_A = 0,
> +	DPLL_ID_PCH_PLL_B = 1,
> +	DPLL_ID_WRPLL1 = 0,
> +	DPLL_ID_WRPLL2 = 1,
>  };
>  #define I915_NUM_PLLS 2
>  
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index cc03f0af517b..8316e0e624a4 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -653,9 +653,11 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
>  		if (reg == WRPLL_CTL1) {
>  			plls->wrpll1_refcount++;
>  			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
> +			intel_crtc->config.shared_dpll = DPLL_ID_WRPLL1;
>  		} else {
>  			plls->wrpll2_refcount++;
>  			intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
> +			intel_crtc->config.shared_dpll = DPLL_ID_WRPLL2;
>  		}
>  	}
>  
> @@ -1183,10 +1185,25 @@ int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
>  	}
>  }
>  
> +static char *hsw_ddi_pll_names[] = {
> +	"WRPLL 1",
> +	"WRPLL 2",
> +};
> +

static const char * const

>  void intel_ddi_pll_init(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	uint32_t val = I915_READ(LCPLL_CTL);
> +	int i;
> +
> +	/* Dummy setup until everything is moved over to avoid upsetting the hw
> +	 * state cross checker. */
> +	dev_priv->num_shared_dpll = 0;
> +
> +	for (i = 0; i < 2; i++) {
> +		dev_priv->shared_dplls[i].id = i;
> +		dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
> +	}
>  
>  	/* The LCPLL register should be turned on by the BIOS. For now let's
>  	 * just check its state and print errors in case something is wrong.
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 1601da1b57a1..fc7cd89b8921 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7019,6 +7019,16 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
>  	port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
>  
>  	pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
> +
> +	switch (pipe_config->ddi_pll_sel) {
> +	case PORT_CLK_SEL_WRPLL1:
> +		pipe_config->shared_dpll = DPLL_ID_WRPLL1;
> +		break;
> +	case PORT_CLK_SEL_WRPLL2:
> +		pipe_config->shared_dpll = DPLL_ID_WRPLL2;
> +		break;
> +	}
> +
>  	/*
>  	 * Haswell has only FDI/PCH transcoder A. It is which is connected to
>  	 * DDI E. So just check whether this pipe is wired to DDI E and whether
> @@ -10340,12 +10350,6 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
>  	.page_flip = intel_crtc_page_flip,
>  };
>  
> -static void intel_cpu_pll_init(struct drm_device *dev)
> -{
> -	if (HAS_DDI(dev))
> -		intel_ddi_pll_init(dev);
> -}
> -
>  static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
>  				      struct intel_shared_dpll *pll,
>  				      struct intel_dpll_hw_state *hw_state)
> @@ -10433,7 +10437,9 @@ static void intel_shared_dpll_init(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
> +	if (HAS_DDI(dev))
> +		intel_ddi_pll_init(dev);
> +	else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
>  		ibx_pch_dpll_init(dev);
>  	else
>  		dev_priv->num_shared_dpll = 0;
> @@ -11232,7 +11238,6 @@ void intel_modeset_init(struct drm_device *dev)
>  	intel_init_dpio(dev);
>  	intel_reset_dpio(dev);
>  
> -	intel_cpu_pll_init(dev);
>  	intel_shared_dpll_init(dev);
>  
>  	/* Just disable it once at startup */
> -- 
> 1.8.1.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx