From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 58/66] drm/i915: Precompute static
 ddi_pll_sel values in encoders
Date: Tue, 20 May 2014 13:27:25 +0200
Message-ID: <20140520112725.GQ8790@phenom.ffwll.local>
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To: Damien Lespiau <damien.lespiau@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>, Intel Graphics Development <intel-gfx@lists.freedesktop.org>
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On Tue, May 20, 2014 at 11:56:28AM +0100, Damien Lespiau wrote:
> On Thu, Apr 24, 2014 at 11:55:34PM +0200, Daniel Vetter wrote:
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -272,6 +272,7 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
> >  			I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
> >  			POSTING_READ(WRPLL_CTL1);
> >  		}
> > +		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
> >  		break;
> >  	case PORT_CLK_SEL_WRPLL2:
> >  		plls->wrpll2_refcount--;
> > @@ -282,13 +283,12 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
> >  			I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
> >  			POSTING_READ(WRPLL_CTL2);
> >  		}
> > +		intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
> >  		break;
> >  	}
> >  
> >  	WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
> >  	WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
> > -
> > -	intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
> >  }
> 
> Who sets config.ddi_pll_sel to NONE for VGA and DP now?

We don't care about that any more. The spll handling was completely moved
into intel_crt.c with the intermediate patches, and intel DP directly keys
off the right clock from config->port_clock.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch