* [PATCH 1/6] drm/i915: Drop bogus comments about display reset
2014-05-19 16:23 [PATCH 0/6] drm/i915: g4x/ilk reset fixes ville.syrjala
@ 2014-05-19 16:23 ` ville.syrjala
2014-05-19 16:29 ` Jesse Barnes
2014-05-19 16:23 ` [PATCH 2/6] drm/i915: Fix ILK reset wait ville.syrjala
` (4 subsequent siblings)
5 siblings, 1 reply; 17+ messages in thread
From: ville.syrjala @ 2014-05-19 16:23 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
There are comments in the gen4-5 reset functions stating that we can't
reset render and media without also doing a display reset. But that's
exactly what the code does, ie. we don't perform a display reset. Drop
the bogus comments.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 27fe2df..0e333f2 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -978,7 +978,6 @@ static int i965_do_reset(struct drm_device *dev)
if (ret)
return ret;
- /* We can't reset render&media without also resetting display ... */
pci_write_config_byte(dev->pdev, I965_GDRST,
GRDOM_MEDIA | GRDOM_RESET_ENABLE);
@@ -1005,7 +1004,6 @@ static int ironlake_do_reset(struct drm_device *dev)
if (ret)
return ret;
- /* We can't reset render&media without also resetting display ... */
gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
gdrst &= ~GRDOM_MASK;
I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
--
1.8.5.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 1/6] drm/i915: Drop bogus comments about display reset
2014-05-19 16:23 ` [PATCH 1/6] drm/i915: Drop bogus comments about display reset ville.syrjala
@ 2014-05-19 16:29 ` Jesse Barnes
0 siblings, 0 replies; 17+ messages in thread
From: Jesse Barnes @ 2014-05-19 16:29 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Mon, 19 May 2014 19:23:22 +0300
ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> There are comments in the gen4-5 reset functions stating that we can't
> reset render and media without also doing a display reset. But that's
> exactly what the code does, ie. we don't perform a display reset. Drop
> the bogus comments.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 27fe2df..0e333f2 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -978,7 +978,6 @@ static int i965_do_reset(struct drm_device *dev)
> if (ret)
> return ret;
>
> - /* We can't reset render&media without also resetting display ... */
> pci_write_config_byte(dev->pdev, I965_GDRST,
> GRDOM_MEDIA | GRDOM_RESET_ENABLE);
>
> @@ -1005,7 +1004,6 @@ static int ironlake_do_reset(struct drm_device *dev)
> if (ret)
> return ret;
>
> - /* We can't reset render&media without also resetting display ... */
> gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
> gdrst &= ~GRDOM_MASK;
> I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
--
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/6] drm/i915: Fix ILK reset wait
2014-05-19 16:23 [PATCH 0/6] drm/i915: g4x/ilk reset fixes ville.syrjala
2014-05-19 16:23 ` [PATCH 1/6] drm/i915: Drop bogus comments about display reset ville.syrjala
@ 2014-05-19 16:23 ` ville.syrjala
2014-05-19 16:30 ` Jesse Barnes
2014-05-19 16:23 ` [PATCH 3/6] drm/i915: Fix ILK GPU reset domain bits ville.syrjala
` (3 subsequent siblings)
5 siblings, 1 reply; 17+ messages in thread
From: ville.syrjala @ 2014-05-19 16:23 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We should be waiting for the reset bit to clear, not remain set.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 0e333f2..d79db88 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1000,7 +1000,8 @@ static int ironlake_do_reset(struct drm_device *dev)
gdrst &= ~GRDOM_MASK;
I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
- ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
+ ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
+ GRDOM_RESET_ENABLE) == 0, 500);
if (ret)
return ret;
@@ -1008,7 +1009,8 @@ static int ironlake_do_reset(struct drm_device *dev)
gdrst &= ~GRDOM_MASK;
I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
- return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
+ return wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
+ GRDOM_RESET_ENABLE) == 0, 500);
}
static int gen6_do_reset(struct drm_device *dev)
--
1.8.5.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 2/6] drm/i915: Fix ILK reset wait
2014-05-19 16:23 ` [PATCH 2/6] drm/i915: Fix ILK reset wait ville.syrjala
@ 2014-05-19 16:30 ` Jesse Barnes
2014-05-20 8:01 ` Daniel Vetter
0 siblings, 1 reply; 17+ messages in thread
From: Jesse Barnes @ 2014-05-19 16:30 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Mon, 19 May 2014 19:23:23 +0300
ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We should be waiting for the reset bit to clear, not remain set.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 0e333f2..d79db88 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1000,7 +1000,8 @@ static int ironlake_do_reset(struct drm_device *dev)
> gdrst &= ~GRDOM_MASK;
> I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
> gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
> - ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
> + ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
> + GRDOM_RESET_ENABLE) == 0, 500);
> if (ret)
> return ret;
>
> @@ -1008,7 +1009,8 @@ static int ironlake_do_reset(struct drm_device *dev)
> gdrst &= ~GRDOM_MASK;
> I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
> gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
> - return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
> + return wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
> + GRDOM_RESET_ENABLE) == 0, 500);
> }
>
> static int gen6_do_reset(struct drm_device *dev)
Arg, I lost the docs on this, but it matches what I remember.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
--
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/6] drm/i915: Fix ILK reset wait
2014-05-19 16:30 ` Jesse Barnes
@ 2014-05-20 8:01 ` Daniel Vetter
2014-05-20 8:18 ` Ville Syrjälä
0 siblings, 1 reply; 17+ messages in thread
From: Daniel Vetter @ 2014-05-20 8:01 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On Mon, May 19, 2014 at 09:30:25AM -0700, Jesse Barnes wrote:
> On Mon, 19 May 2014 19:23:23 +0300
> ville.syrjala@linux.intel.com wrote:
>
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > We should be waiting for the reset bit to clear, not remain set.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_uncore.c | 6 ++++--
> > 1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> > index 0e333f2..d79db88 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -1000,7 +1000,8 @@ static int ironlake_do_reset(struct drm_device *dev)
> > gdrst &= ~GRDOM_MASK;
> > I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
> > gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
> > - ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
> > + ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
> > + GRDOM_RESET_ENABLE) == 0, 500);
> > if (ret)
> > return ret;
> >
> > @@ -1008,7 +1009,8 @@ static int ironlake_do_reset(struct drm_device *dev)
> > gdrst &= ~GRDOM_MASK;
> > I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
> > gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
> > - return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
> > + return wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
> > + GRDOM_RESET_ENABLE) == 0, 500);
> > }
> >
> > static int gen6_do_reset(struct drm_device *dev)
>
> Arg, I lost the docs on this, but it matches what I remember.
>
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Was this tested on an ilk? I remember writing a similar patch and I didn't
apply it due to conflict with reality.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/6] drm/i915: Fix ILK reset wait
2014-05-20 8:01 ` Daniel Vetter
@ 2014-05-20 8:18 ` Ville Syrjälä
2014-05-20 8:43 ` Daniel Vetter
0 siblings, 1 reply; 17+ messages in thread
From: Ville Syrjälä @ 2014-05-20 8:18 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Tue, May 20, 2014 at 10:01:27AM +0200, Daniel Vetter wrote:
> On Mon, May 19, 2014 at 09:30:25AM -0700, Jesse Barnes wrote:
> > On Mon, 19 May 2014 19:23:23 +0300
> > ville.syrjala@linux.intel.com wrote:
> >
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > We should be waiting for the reset bit to clear, not remain set.
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_uncore.c | 6 ++++--
> > > 1 file changed, 4 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> > > index 0e333f2..d79db88 100644
> > > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > > @@ -1000,7 +1000,8 @@ static int ironlake_do_reset(struct drm_device *dev)
> > > gdrst &= ~GRDOM_MASK;
> > > I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
> > > gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
> > > - ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
> > > + ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
> > > + GRDOM_RESET_ENABLE) == 0, 500);
> > > if (ret)
> > > return ret;
> > >
> > > @@ -1008,7 +1009,8 @@ static int ironlake_do_reset(struct drm_device *dev)
> > > gdrst &= ~GRDOM_MASK;
> > > I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
> > > gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
> > > - return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
> > > + return wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
> > > + GRDOM_RESET_ENABLE) == 0, 500);
> > > }
> > >
> > > static int gen6_do_reset(struct drm_device *dev)
> >
> > Arg, I lost the docs on this, but it matches what I remember.
> >
> > Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>
> Was this tested on an ilk? I remember writing a similar patch and I didn't
> apply it due to conflict with reality.
Yes. My ILK seems happy now. Maybe your ILK barfed on it due to
specifying invalid reset domains (fixed in 3/6)?
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/6] drm/i915: Fix ILK reset wait
2014-05-20 8:18 ` Ville Syrjälä
@ 2014-05-20 8:43 ` Daniel Vetter
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Vetter @ 2014-05-20 8:43 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, May 20, 2014 at 11:18:44AM +0300, Ville Syrjälä wrote:
> On Tue, May 20, 2014 at 10:01:27AM +0200, Daniel Vetter wrote:
> > On Mon, May 19, 2014 at 09:30:25AM -0700, Jesse Barnes wrote:
> > > On Mon, 19 May 2014 19:23:23 +0300
> > > ville.syrjala@linux.intel.com wrote:
> > >
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > >
> > > > We should be waiting for the reset bit to clear, not remain set.
> > > >
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/intel_uncore.c | 6 ++++--
> > > > 1 file changed, 4 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> > > > index 0e333f2..d79db88 100644
> > > > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > > > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > > > @@ -1000,7 +1000,8 @@ static int ironlake_do_reset(struct drm_device *dev)
> > > > gdrst &= ~GRDOM_MASK;
> > > > I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
> > > > gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
> > > > - ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
> > > > + ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
> > > > + GRDOM_RESET_ENABLE) == 0, 500);
> > > > if (ret)
> > > > return ret;
> > > >
> > > > @@ -1008,7 +1009,8 @@ static int ironlake_do_reset(struct drm_device *dev)
> > > > gdrst &= ~GRDOM_MASK;
> > > > I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
> > > > gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
> > > > - return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
> > > > + return wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
> > > > + GRDOM_RESET_ENABLE) == 0, 500);
> > > > }
> > > >
> > > > static int gen6_do_reset(struct drm_device *dev)
> > >
> > > Arg, I lost the docs on this, but it matches what I remember.
> > >
> > > Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> >
> > Was this tested on an ilk? I remember writing a similar patch and I didn't
> > apply it due to conflict with reality.
>
> Yes. My ILK seems happy now. Maybe your ILK barfed on it due to
> specifying invalid reset domains (fixed in 3/6)?
That might indeed explain what I've seen. Both patches applied, thanks.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 3/6] drm/i915: Fix ILK GPU reset domain bits
2014-05-19 16:23 [PATCH 0/6] drm/i915: g4x/ilk reset fixes ville.syrjala
2014-05-19 16:23 ` [PATCH 1/6] drm/i915: Drop bogus comments about display reset ville.syrjala
2014-05-19 16:23 ` [PATCH 2/6] drm/i915: Fix ILK reset wait ville.syrjala
@ 2014-05-19 16:23 ` ville.syrjala
2014-05-19 16:32 ` Jesse Barnes
2014-05-19 16:23 ` [PATCH 4/6] drm/i915: Kill RMW from ILK reset code ville.syrjala
` (2 subsequent siblings)
5 siblings, 1 reply; 17+ messages in thread
From: ville.syrjala @ 2014-05-19 16:23 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We're using the reset domains bits for g4x on ilk. But on ilk those bits
actually shifted by one bit. Fix it up so that we use the correct bits.
We were actually always writing 0x2 to the reset domain bits, which
is a reserved value. In practice it looks like the hardware ignores that
value since nothing happens if I write that value when there's a 3D
workload running. Writing the _correct_ render domain value actually
makes the GPU stop.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 +++++++-
drivers/gpu/drm/i915/intel_uncore.c | 12 ++++++------
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ac90786..6522af4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -79,13 +79,19 @@
/* Graphics reset regs */
#define I965_GDRST 0xc0 /* PCI config register */
-#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
#define GRDOM_FULL (0<<2)
#define GRDOM_RENDER (1<<2)
#define GRDOM_MEDIA (3<<2)
#define GRDOM_MASK (3<<2)
#define GRDOM_RESET_ENABLE (1<<0)
+#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
+#define ILK_GRDOM_FULL (0<<1)
+#define ILK_GRDOM_RENDER (1<<1)
+#define ILK_GRDOM_MEDIA (3<<1)
+#define ILK_GRDOM_MASK (3<<1)
+#define ILK_GRDOM_RESET_ENABLE (1<<0)
+
#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
#define GEN6_MBC_SNPCR_SHIFT 21
#define GEN6_MBC_SNPCR_MASK (3<<21)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index d79db88..008d30b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -997,20 +997,20 @@ static int ironlake_do_reset(struct drm_device *dev)
int ret;
gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
- gdrst &= ~GRDOM_MASK;
+ gdrst &= ~ILK_GRDOM_MASK;
I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
- gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
+ gdrst | ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
- GRDOM_RESET_ENABLE) == 0, 500);
+ ILK_GRDOM_RESET_ENABLE) == 0, 500);
if (ret)
return ret;
gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
- gdrst &= ~GRDOM_MASK;
+ gdrst &= ~ILK_GRDOM_MASK;
I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
- gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
+ gdrst | ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
return wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
- GRDOM_RESET_ENABLE) == 0, 500);
+ ILK_GRDOM_RESET_ENABLE) == 0, 500);
}
static int gen6_do_reset(struct drm_device *dev)
--
1.8.5.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 3/6] drm/i915: Fix ILK GPU reset domain bits
2014-05-19 16:23 ` [PATCH 3/6] drm/i915: Fix ILK GPU reset domain bits ville.syrjala
@ 2014-05-19 16:32 ` Jesse Barnes
0 siblings, 0 replies; 17+ messages in thread
From: Jesse Barnes @ 2014-05-19 16:32 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Mon, 19 May 2014 19:23:24 +0300
ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We're using the reset domains bits for g4x on ilk. But on ilk those bits
> actually shifted by one bit. Fix it up so that we use the correct bits.
>
> We were actually always writing 0x2 to the reset domain bits, which
> is a reserved value. In practice it looks like the hardware ignores that
> value since nothing happens if I write that value when there's a 3D
> workload running. Writing the _correct_ render domain value actually
> makes the GPU stop.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 8 +++++++-
> drivers/gpu/drm/i915/intel_uncore.c | 12 ++++++------
> 2 files changed, 13 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ac90786..6522af4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -79,13 +79,19 @@
>
> /* Graphics reset regs */
> #define I965_GDRST 0xc0 /* PCI config register */
> -#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
> #define GRDOM_FULL (0<<2)
> #define GRDOM_RENDER (1<<2)
> #define GRDOM_MEDIA (3<<2)
> #define GRDOM_MASK (3<<2)
> #define GRDOM_RESET_ENABLE (1<<0)
>
> +#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
> +#define ILK_GRDOM_FULL (0<<1)
> +#define ILK_GRDOM_RENDER (1<<1)
> +#define ILK_GRDOM_MEDIA (3<<1)
> +#define ILK_GRDOM_MASK (3<<1)
> +#define ILK_GRDOM_RESET_ENABLE (1<<0)
> +
> #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
> #define GEN6_MBC_SNPCR_SHIFT 21
> #define GEN6_MBC_SNPCR_MASK (3<<21)
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index d79db88..008d30b 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -997,20 +997,20 @@ static int ironlake_do_reset(struct drm_device *dev)
> int ret;
>
> gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
> - gdrst &= ~GRDOM_MASK;
> + gdrst &= ~ILK_GRDOM_MASK;
> I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
> - gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
> + gdrst | ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
> ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
> - GRDOM_RESET_ENABLE) == 0, 500);
> + ILK_GRDOM_RESET_ENABLE) == 0, 500);
> if (ret)
> return ret;
>
> gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
> - gdrst &= ~GRDOM_MASK;
> + gdrst &= ~ILK_GRDOM_MASK;
> I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
> - gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
> + gdrst | ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
> return wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
> - GRDOM_RESET_ENABLE) == 0, 500);
> + ILK_GRDOM_RESET_ENABLE) == 0, 500);
> }
>
> static int gen6_do_reset(struct drm_device *dev)
Can't find docs, but if you tested that wins anyway.
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
--
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 4/6] drm/i915: Kill RMW from ILK reset code
2014-05-19 16:23 [PATCH 0/6] drm/i915: g4x/ilk reset fixes ville.syrjala
` (2 preceding siblings ...)
2014-05-19 16:23 ` [PATCH 3/6] drm/i915: Fix ILK GPU reset domain bits ville.syrjala
@ 2014-05-19 16:23 ` ville.syrjala
2014-05-20 18:37 ` Jesse Barnes
2014-05-19 16:23 ` [PATCH 5/6] drm/i915: Clear GDSR after reset on ILK ville.syrjala
2014-05-19 16:23 ` [PATCH 6/6] drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elk ville.syrjala
5 siblings, 1 reply; 17+ messages in thread
From: ville.syrjala @ 2014-05-19 16:23 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
All the other bits in the GDSR register are read-only, so we don't have
to preserve them when we perform a GPU reset.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 008d30b..5c29cfe 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -993,22 +993,17 @@ static int i965_do_reset(struct drm_device *dev)
static int ironlake_do_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- u32 gdrst;
int ret;
- gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
- gdrst &= ~ILK_GRDOM_MASK;
I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
- gdrst | ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
+ ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
ILK_GRDOM_RESET_ENABLE) == 0, 500);
if (ret)
return ret;
- gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
- gdrst &= ~ILK_GRDOM_MASK;
I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
- gdrst | ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
+ ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
return wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
ILK_GRDOM_RESET_ENABLE) == 0, 500);
}
--
1.8.5.5
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 4/6] drm/i915: Kill RMW from ILK reset code
2014-05-19 16:23 ` [PATCH 4/6] drm/i915: Kill RMW from ILK reset code ville.syrjala
@ 2014-05-20 18:37 ` Jesse Barnes
0 siblings, 0 replies; 17+ messages in thread
From: Jesse Barnes @ 2014-05-20 18:37 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Mon, 19 May 2014 19:23:25 +0300
ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> All the other bits in the GDSR register are read-only, so we don't have
> to preserve them when we perform a GPU reset.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 9 ++-------
> 1 file changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 008d30b..5c29cfe 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -993,22 +993,17 @@ static int i965_do_reset(struct drm_device *dev)
> static int ironlake_do_reset(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> - u32 gdrst;
> int ret;
>
> - gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
> - gdrst &= ~ILK_GRDOM_MASK;
> I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
> - gdrst | ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
> + ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
> ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
> ILK_GRDOM_RESET_ENABLE) == 0, 500);
> if (ret)
> return ret;
>
> - gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
> - gdrst &= ~ILK_GRDOM_MASK;
> I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
> - gdrst | ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
> + ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
> return wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
> ILK_GRDOM_RESET_ENABLE) == 0, 500);
> }
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
--
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 5/6] drm/i915: Clear GDSR after reset on ILK
2014-05-19 16:23 [PATCH 0/6] drm/i915: g4x/ilk reset fixes ville.syrjala
` (3 preceding siblings ...)
2014-05-19 16:23 ` [PATCH 4/6] drm/i915: Kill RMW from ILK reset code ville.syrjala
@ 2014-05-19 16:23 ` ville.syrjala
2014-05-20 18:38 ` Jesse Barnes
2014-05-19 16:23 ` [PATCH 6/6] drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elk ville.syrjala
5 siblings, 1 reply; 17+ messages in thread
From: ville.syrjala @ 2014-05-19 16:23 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Clear the reset domain after a succesful GPU reset on ilk. We already
do that on gen4, so let's try to be a bit more consistent. And if
ether render or media reset fails, we might use the leftover value
in the register to pinpoint the culprit.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 5c29cfe..cd0d6e2 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1004,8 +1004,14 @@ static int ironlake_do_reset(struct drm_device *dev)
I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
- return wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
- ILK_GRDOM_RESET_ENABLE) == 0, 500);
+ ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
+ ILK_GRDOM_RESET_ENABLE) == 0, 500);
+ if (ret)
+ return ret;
+
+ I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0);
+
+ return 0;
}
static int gen6_do_reset(struct drm_device *dev)
--
1.8.5.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 5/6] drm/i915: Clear GDSR after reset on ILK
2014-05-19 16:23 ` [PATCH 5/6] drm/i915: Clear GDSR after reset on ILK ville.syrjala
@ 2014-05-20 18:38 ` Jesse Barnes
0 siblings, 0 replies; 17+ messages in thread
From: Jesse Barnes @ 2014-05-20 18:38 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Mon, 19 May 2014 19:23:26 +0300
ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Clear the reset domain after a succesful GPU reset on ilk. We already
> do that on gen4, so let's try to be a bit more consistent. And if
> ether render or media reset fails, we might use the leftover value
> in the register to pinpoint the culprit.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 5c29cfe..cd0d6e2 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1004,8 +1004,14 @@ static int ironlake_do_reset(struct drm_device *dev)
>
> I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
> ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
> - return wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
> - ILK_GRDOM_RESET_ENABLE) == 0, 500);
> + ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
> + ILK_GRDOM_RESET_ENABLE) == 0, 500);
> + if (ret)
> + return ret;
> +
> + I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0);
> +
> + return 0;
> }
>
> static int gen6_do_reset(struct drm_device *dev)
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
--
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 6/6] drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elk
2014-05-19 16:23 [PATCH 0/6] drm/i915: g4x/ilk reset fixes ville.syrjala
` (4 preceding siblings ...)
2014-05-19 16:23 ` [PATCH 5/6] drm/i915: Clear GDSR after reset on ILK ville.syrjala
@ 2014-05-19 16:23 ` ville.syrjala
2014-05-20 18:46 ` Jesse Barnes
5 siblings, 1 reply; 17+ messages in thread
From: ville.syrjala @ 2014-05-19 16:23 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Apparently we need to disable VCP unit clock gating around media reset
on g4x.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
drivers/gpu/drm/i915/intel_uncore.c | 36 +++++++++++++++++++++++++++++++++++-
2 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6522af4..543f23c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1724,6 +1724,10 @@ enum punit_power_well {
#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
+
+#define VDECCLK_GATE_D 0x620C /* g4x only */
+#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
+
#define RAMCLK_GATE_D 0x6210 /* CRL only */
#define DEUC 0x6214 /* CRL only */
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index cd0d6e2..67385a9 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -990,6 +990,36 @@ static int i965_do_reset(struct drm_device *dev)
return 0;
}
+static int g4x_do_reset(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int ret;
+
+ pci_write_config_byte(dev->pdev, I965_GDRST,
+ GRDOM_RENDER | GRDOM_RESET_ENABLE);
+ ret = wait_for(i965_reset_complete(dev), 500);
+ if (ret)
+ return ret;
+
+ /* WaVcpClkGateDisableForMediaReset:ctg,elk */
+ I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
+ POSTING_READ(VDECCLK_GATE_D);
+
+ pci_write_config_byte(dev->pdev, I965_GDRST,
+ GRDOM_MEDIA | GRDOM_RESET_ENABLE);
+ ret = wait_for(i965_reset_complete(dev), 500);
+ if (ret)
+ return ret;
+
+ /* WaVcpClkGateDisableForMediaReset:ctg,elk */
+ I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
+ POSTING_READ(VDECCLK_GATE_D);
+
+ pci_write_config_byte(dev->pdev, I965_GDRST, 0);
+
+ return 0;
+}
+
static int ironlake_do_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1042,7 +1072,11 @@ int intel_gpu_reset(struct drm_device *dev)
case 7:
case 6: return gen6_do_reset(dev);
case 5: return ironlake_do_reset(dev);
- case 4: return i965_do_reset(dev);
+ case 4:
+ if (IS_G4X(dev))
+ return g4x_do_reset(dev);
+ else
+ return i965_do_reset(dev);
default: return -ENODEV;
}
}
--
1.8.5.5
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^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 6/6] drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elk
2014-05-19 16:23 ` [PATCH 6/6] drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elk ville.syrjala
@ 2014-05-20 18:46 ` Jesse Barnes
2014-05-22 14:35 ` Daniel Vetter
0 siblings, 1 reply; 17+ messages in thread
From: Jesse Barnes @ 2014-05-20 18:46 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Mon, 19 May 2014 19:23:27 +0300
ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Apparently we need to disable VCP unit clock gating around media reset
> on g4x.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> drivers/gpu/drm/i915/intel_uncore.c | 36 +++++++++++++++++++++++++++++++++++-
> 2 files changed, 39 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6522af4..543f23c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1724,6 +1724,10 @@ enum punit_power_well {
> #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
> #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
> #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
> +
> +#define VDECCLK_GATE_D 0x620C /* g4x only */
> +#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
> +
> #define RAMCLK_GATE_D 0x6210 /* CRL only */
> #define DEUC 0x6214 /* CRL only */
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index cd0d6e2..67385a9 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -990,6 +990,36 @@ static int i965_do_reset(struct drm_device *dev)
> return 0;
> }
>
> +static int g4x_do_reset(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + int ret;
> +
> + pci_write_config_byte(dev->pdev, I965_GDRST,
> + GRDOM_RENDER | GRDOM_RESET_ENABLE);
> + ret = wait_for(i965_reset_complete(dev), 500);
> + if (ret)
> + return ret;
> +
> + /* WaVcpClkGateDisableForMediaReset:ctg,elk */
> + I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
> + POSTING_READ(VDECCLK_GATE_D);
> +
> + pci_write_config_byte(dev->pdev, I965_GDRST,
> + GRDOM_MEDIA | GRDOM_RESET_ENABLE);
> + ret = wait_for(i965_reset_complete(dev), 500);
> + if (ret)
> + return ret;
> +
> + /* WaVcpClkGateDisableForMediaReset:ctg,elk */
> + I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
> + POSTING_READ(VDECCLK_GATE_D);
> +
> + pci_write_config_byte(dev->pdev, I965_GDRST, 0);
> +
> + return 0;
> +}
> +
> static int ironlake_do_reset(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -1042,7 +1072,11 @@ int intel_gpu_reset(struct drm_device *dev)
> case 7:
> case 6: return gen6_do_reset(dev);
> case 5: return ironlake_do_reset(dev);
> - case 4: return i965_do_reset(dev);
> + case 4:
> + if (IS_G4X(dev))
> + return g4x_do_reset(dev);
> + else
> + return i965_do_reset(dev);
> default: return -ENODEV;
> }
> }
Given how the reset flow stuff works this seems sensible, but I
couldn't find it in the docs I have. Shouldn't do any harm at the very
worst...
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
--
Jesse Barnes, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 6/6] drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elk
2014-05-20 18:46 ` Jesse Barnes
@ 2014-05-22 14:35 ` Daniel Vetter
0 siblings, 0 replies; 17+ messages in thread
From: Daniel Vetter @ 2014-05-22 14:35 UTC (permalink / raw)
To: Jesse Barnes; +Cc: intel-gfx
On Tue, May 20, 2014 at 11:46:45AM -0700, Jesse Barnes wrote:
> On Mon, 19 May 2014 19:23:27 +0300
> ville.syrjala@linux.intel.com wrote:
>
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Apparently we need to disable VCP unit clock gating around media reset
> > on g4x.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> > drivers/gpu/drm/i915/intel_uncore.c | 36 +++++++++++++++++++++++++++++++++++-
> > 2 files changed, 39 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 6522af4..543f23c 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1724,6 +1724,10 @@ enum punit_power_well {
> > #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
> > #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
> > #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
> > +
> > +#define VDECCLK_GATE_D 0x620C /* g4x only */
> > +#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
> > +
> > #define RAMCLK_GATE_D 0x6210 /* CRL only */
> > #define DEUC 0x6214 /* CRL only */
> >
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> > index cd0d6e2..67385a9 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -990,6 +990,36 @@ static int i965_do_reset(struct drm_device *dev)
> > return 0;
> > }
> >
> > +static int g4x_do_reset(struct drm_device *dev)
> > +{
> > + struct drm_i915_private *dev_priv = dev->dev_private;
> > + int ret;
> > +
> > + pci_write_config_byte(dev->pdev, I965_GDRST,
> > + GRDOM_RENDER | GRDOM_RESET_ENABLE);
> > + ret = wait_for(i965_reset_complete(dev), 500);
> > + if (ret)
> > + return ret;
> > +
> > + /* WaVcpClkGateDisableForMediaReset:ctg,elk */
> > + I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
> > + POSTING_READ(VDECCLK_GATE_D);
> > +
> > + pci_write_config_byte(dev->pdev, I965_GDRST,
> > + GRDOM_MEDIA | GRDOM_RESET_ENABLE);
> > + ret = wait_for(i965_reset_complete(dev), 500);
> > + if (ret)
> > + return ret;
> > +
> > + /* WaVcpClkGateDisableForMediaReset:ctg,elk */
> > + I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
> > + POSTING_READ(VDECCLK_GATE_D);
> > +
> > + pci_write_config_byte(dev->pdev, I965_GDRST, 0);
> > +
> > + return 0;
> > +}
> > +
> > static int ironlake_do_reset(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -1042,7 +1072,11 @@ int intel_gpu_reset(struct drm_device *dev)
> > case 7:
> > case 6: return gen6_do_reset(dev);
> > case 5: return ironlake_do_reset(dev);
> > - case 4: return i965_do_reset(dev);
> > + case 4:
> > + if (IS_G4X(dev))
> > + return g4x_do_reset(dev);
> > + else
> > + return i965_do_reset(dev);
> > default: return -ENODEV;
> > }
> > }
>
> Given how the reset flow stuff works this seems sensible, but I
> couldn't find it in the docs I have. Shouldn't do any harm at the very
> worst...
>
> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
I want the g4x/i965 split, so also merged this one here ;-)
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 17+ messages in thread