Re: [PATCH 38/66] drm/i915: s/ironlake_/intel_ for the enable_share_dpll function

[Daniel Vetter <daniel@ffwll.ch>]

On Tue, May 20, 2014 at 11:29:54AM +0100, Damien Lespiau wrote:
> On Thu, Apr 24, 2014 at 11:55:14PM +0200, Daniel Vetter wrote:
> > Besides the fairly useless BUG_ON the logic is completely generic
> > and cane be used on any platform what wants to reuse the shared
> > dpll support code.
> > 
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

Queued up to this patch, thanks everyone for the review.
-Daniel

> 
> -- 
> Damien
> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 8 +++-----
> >  1 file changed, 3 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 96bab640399f..1513d9fceebe 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1568,21 +1568,19 @@ static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
> >  }
> >  
> >  /**
> > - * ironlake_enable_shared_dpll - enable PCH PLL
> > + * intel_enable_shared_dpll - enable PCH PLL
> >   * @dev_priv: i915 private structure
> >   * @pipe: pipe PLL to enable
> >   *
> >   * The PCH PLL needs to be enabled before the PCH transcoder, since it
> >   * drives the transcoder clock.
> >   */
> > -static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
> > +static void intel_enable_shared_dpll(struct intel_crtc *crtc)
> >  {
> >  	struct drm_device *dev = crtc->base.dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
> >  
> > -	/* PCH PLLs only available on ILK, SNB and IVB */
> > -	BUG_ON(INTEL_INFO(dev)->gen < 5);
> >  	if (WARN_ON(pll == NULL))
> >  		return;
> >  
> > @@ -3328,7 +3326,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
> >  	 * Note that enable_shared_dpll tries to do the right thing, but
> >  	 * get_shared_dpll unconditionally resets the pll - we need that to have
> >  	 * the right LVDS enable sequence. */
> > -	ironlake_enable_shared_dpll(intel_crtc);
> > +	intel_enable_shared_dpll(intel_crtc);
> >  
> >  	/* set transcoder timing, panel must allow it */
> >  	assert_panel_unlocked(dev_priv, pipe);
> > -- 
> > 1.8.1.4
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch