From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 42/71] drm/i915/chv: Implement WaDisableSamplerPowerBypass for CHV Date: Tue, 20 May 2014 15:21:31 +0200 Message-ID: <20140520132131.GT8790@phenom.ffwll.local> References: <1397039349-10639-1-git-send-email-ville.syrjala@linux.intel.com> <1397039349-10639-43-git-send-email-ville.syrjala@linux.intel.com> <20140428082311.GW18465@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ee0-f46.google.com (mail-ee0-f46.google.com [74.125.83.46]) by gabe.freedesktop.org (Postfix) with ESMTP id 04D9F6E7F3 for ; Tue, 20 May 2014 06:21:35 -0700 (PDT) Received: by mail-ee0-f46.google.com with SMTP id t10so593304eei.33 for ; Tue, 20 May 2014 06:21:35 -0700 (PDT) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Paulo Zanoni Cc: Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Mon, Apr 28, 2014 at 07:19:50PM -0300, Paulo Zanoni wrote: > 2014-04-28 5:23 GMT-03:00 Ville Syrj=E4l=E4 : > > On Fri, Apr 25, 2014 at 05:55:38PM -0300, Paulo Zanoni wrote: > >> 2014-04-09 7:28 GMT-03:00 : > >> > From: Rafael Barbalho > >> > > >> > Cherryview also needs this WA. > >> > >> At least on the chv_rebase tree, this WA is implemented for BDW but it > >> is not documented as pre-prod only, and its name is not there. We > >> should probably add a comment documenting the name and the fact that > >> it is also pre-prod on BDW. > > > > IIRC BDW will need it even on production steppings. > = > Hmmm the register documentation says one thing while the WA lists say > others... I'll let you discover which one is correct :) > = > > > > I think I have a patch somewhere that add the w/a note for BDW, but I g= uess > > I didn't post it yet. > > > >> > >> > >> > > >> > Signed-off-by: Rafael Barbalho > >> > [vsyrjala: Looks like it's for pre-prodution hw only] > >> > Signed-off-by: Ville Syrj=E4l=E4 > >> > --- > >> > drivers/gpu/drm/i915/intel_pm.c | 4 ++++ > >> > 1 file changed, 4 insertions(+) > >> > > >> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/= intel_pm.c > >> > index 468fe37..60f876c 100644 > >> > --- a/drivers/gpu/drm/i915/intel_pm.c > >> > +++ b/drivers/gpu/drm/i915/intel_pm.c > >> > @@ -5405,6 +5405,10 @@ static void cherryview_init_clock_gating(stru= ct drm_device *dev) > >> > /* WaDisableSDEUnitClockGating:chv */ > >> > I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | > >> > GEN8_SDEUNIT_CLOCK_GATE_DISABLE); > >> > + > >> > + /* WaDisableSamplerPowerBypass:chv (pre-production hw) */ > >> > + I915_WRITE(HALF_SLICE_CHICKEN3, > >> > + _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS)= ); > >> > >> I could not find information anywhere if this is the correct > >> implementation. Can you please provide me pointers to the doc you > >> used? The links on Collab seem broken. > > > > Just w/a database + bspec are enough for this one. > = > Found it :) > = > Reviewed-by: Paulo Zanoni Merged up to this patch (except for the rps patches). -Daniel > = > > > >> > >> Thanks, > >> Paulo > >> > >> > } > >> > > >> > static void g4x_init_clock_gating(struct drm_device *dev) > >> > -- > >> > 1.8.3.2 > >> > > >> > _______________________________________________ > >> > Intel-gfx mailing list > >> > Intel-gfx@lists.freedesktop.org > >> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > >> > >> > >> > >> -- > >> Paulo Zanoni > > > > -- > > Ville Syrj=E4l=E4 > > Intel OTC > = > = > = > -- = > Paulo Zanoni > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch