From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 51/71] drm/i915/chv: Use valleyview_pipestat_irq_handler() for CHV Date: Tue, 20 May 2014 15:28:51 +0200 Message-ID: <20140520132851.GV8790@phenom.ffwll.local> References: <1397039349-10639-1-git-send-email-ville.syrjala@linux.intel.com> <1397039349-10639-52-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ee0-f49.google.com (mail-ee0-f49.google.com [74.125.83.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 9D1C06E807 for ; Tue, 20 May 2014 06:28:56 -0700 (PDT) Received: by mail-ee0-f49.google.com with SMTP id e53so562511eek.8 for ; Tue, 20 May 2014 06:28:55 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1397039349-10639-52-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Apr 09, 2014 at 01:28:49PM +0300, ville.syrjala@linux.intel.com wro= te: > From: Ville Syrj=E4l=E4 > = > Signed-off-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/i915_irq.c | 91 ++++++++---------------------------= ------ > 1 file changed, 17 insertions(+), 74 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_= irq.c > index 9c18a47..9702fde 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1660,6 +1660,9 @@ static void valleyview_pipestat_irq_handler(struct = drm_device *dev, u32 iir) > case PIPE_B: > iir_bit =3D I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; > break; > + case PIPE_C: > + iir_bit =3D I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; > + break; > } > if (iir & iir_bit) > mask |=3D dev_priv->pipestat_irq_mask[pipe]; > @@ -1771,87 +1774,32 @@ static irqreturn_t cherryview_irq_handler(int irq= , void *arg) > drm_i915_private_t *dev_priv =3D dev->dev_private; > u32 master_ctl, iir; > irqreturn_t ret =3D IRQ_NONE; > - unsigned int pipes =3D 0; > - > - master_ctl =3D I915_READ(GEN8_MASTER_IRQ); > - > - I915_WRITE(GEN8_MASTER_IRQ, 0); > - > - ret =3D gen8_gt_irq_handler(dev, dev_priv, master_ctl); > = > + master_ctl =3D I915_READ(GEN8_MASTER_IRQ) & ~DE_MASTER_IRQ_CONTROL; > iir =3D I915_READ(VLV_IIR); > = > - if (iir & (I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_A_E= VENT_INTERRUPT)) > - pipes |=3D 1 << 0; > - if (iir & (I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_B_E= VENT_INTERRUPT)) > - pipes |=3D 1 << 1; > - if (iir & (I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT | I915_DISPLAY_PIPE_C_E= VENT_INTERRUPT)) > - pipes |=3D 1 << 2; > - > - if (pipes) { > - u32 pipe_stats[I915_MAX_PIPES] =3D {}; > - unsigned long irqflags; > - int pipe; > - > - spin_lock_irqsave(&dev_priv->irq_lock, irqflags); > - for_each_pipe(pipe) { > - unsigned int reg; > - > - if (!(pipes & (1 << pipe))) > - continue; > - > - reg =3D PIPESTAT(pipe); > - pipe_stats[pipe] =3D I915_READ(reg); > - > - /* > - * Clear the PIPE*STAT regs before the IIR > - */ > - if (pipe_stats[pipe] & 0x8000ffff) { > - if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) > - DRM_DEBUG_DRIVER("pipe %c underrun\n", > - pipe_name(pipe)); > - I915_WRITE(reg, pipe_stats[pipe]); > - } > - } > - spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); > - > - for_each_pipe(pipe) { > - if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) > - drm_handle_vblank(dev, pipe); > + if (master_ctl =3D=3D 0 && iir =3D=3D 0) > + return IRQ_NONE; > = > - if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { > - intel_prepare_page_flip(dev, pipe); > - intel_finish_page_flip(dev, pipe); > - } > - } > + I915_WRITE(GEN8_MASTER_IRQ, 0); > = > - if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) > - gmbus_irq_handler(dev); > + gen8_gt_irq_handler(dev, dev_priv, master_ctl); > = > - ret =3D IRQ_HANDLED; > - } > + valleyview_pipestat_irq_handler(dev, iir); > = > /* Consume port. Then clear IIR or we'll miss events */ > if (iir & I915_DISPLAY_PORT_INTERRUPT) { > - u32 hotplug_status =3D I915_READ(PORT_HOTPLUG_STAT); > - > - I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); > - > - DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", > - hotplug_status); > - if (hotplug_status & HOTPLUG_INT_STATUS_I915) > - queue_work(dev_priv->wq, > - &dev_priv->hotplug_work); > - > + i9xx_hpd_irq_handler(dev, iir); Fun conflict here - my version of i9xx_hpd_irq_handler doesn't want an iir argument. Please sanity-check, thanks. -Daniel > ret =3D IRQ_HANDLED; > } > = > - > I915_WRITE(VLV_IIR, iir); > = > I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); > POSTING_READ(GEN8_MASTER_IRQ); > = > + ret =3D IRQ_HANDLED; > + > return ret; > } > = > @@ -3526,12 +3474,10 @@ static int cherryview_irq_postinstall(struct drm_= device *dev) > drm_i915_private_t *dev_priv =3D dev->dev_private; > u32 enable_mask =3D I915_DISPLAY_PORT_INTERRUPT | > I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | > - I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | > I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | > - I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT | > - I915_DISPLAY_PIPE_C_EVENT_INTERRUPT | > - I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT; > - u32 pipestat_enable =3D PLANE_FLIP_DONE_INT_EN_VLV; > + I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; > + u32 pipestat_enable =3D PLANE_FLIP_DONE_INT_STATUS_VLV | > + PIPE_CRC_DONE_INTERRUPT_STATUS; > unsigned long irqflags; > int pipe; > = > @@ -3539,16 +3485,13 @@ static int cherryview_irq_postinstall(struct drm_= device *dev) > * Leave vblank interrupts masked initially. enable/disable will > * toggle them based on usage. > */ > - dev_priv->irq_mask =3D ~enable_mask | > - I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | > - I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT | > - I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT; > + dev_priv->irq_mask =3D ~enable_mask; > = > for_each_pipe(pipe) > I915_WRITE(PIPESTAT(pipe), 0xffff); > = > spin_lock_irqsave(&dev_priv->irq_lock, irqflags); > - i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE); > + i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); > for_each_pipe(pipe) > i915_enable_pipestat(dev_priv, pipe, pipestat_enable); > spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); > -- = > 1.8.3.2 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch