From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 64/71] drm/i915/chv: Don't use PCS group
 access reads
Date: Tue, 20 May 2014 17:11:00 +0300
Message-ID: <20140520141100.GI27580@intel.com>
References: <1397039349-10639-1-git-send-email-ville.syrjala@linux.intel.com>
 <1397039349-10639-65-git-send-email-ville.syrjala@linux.intel.com>
 <20140409161838.GR9262@phenom.ffwll.local>
 <20140409165649.GT18465@intel.com>
 <20140520135002.GY8790@phenom.ffwll.local>
Mime-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Return-path: <intel-gfx-bounces@lists.freedesktop.org>
Received: from mga09.intel.com (mga09.intel.com [134.134.136.24])
 by gabe.freedesktop.org (Postfix) with ESMTP id 65CF589CD8
 for <intel-gfx@lists.freedesktop.org>; Tue, 20 May 2014 07:11:49 -0700 (PDT)
Content-Disposition: inline
In-Reply-To: <20140520135002.GY8790@phenom.ffwll.local>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
 <mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
 <mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Errors-To: intel-gfx-bounces@lists.freedesktop.org
Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Tue, May 20, 2014 at 03:50:02PM +0200, Daniel Vetter wrote:
> On Wed, Apr 09, 2014 at 07:56:50PM +0300, Ville Syrj=E4l=E4 wrote:
> > On Wed, Apr 09, 2014 at 06:18:38PM +0200, Daniel Vetter wrote:
> > > On Wed, Apr 09, 2014 at 01:29:02PM +0300, ville.syrjala@linux.intel.c=
om wrote:
> > > > From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > > > =

> > > > All PCS groups access reads return 0xffffffff, so we can't use group
> > > > access for RMW cycles. Instead target each spline separately.
> > > =

> > > I have no idea what PCS means here and spline ... Can you please expa=
nd
> > > for those who haven't yet lost their souls in chv docs? Just so we ha=
ve a
> > > commonly-understood jargon for talking about this stuff.
> > =

> > I guess we should have that somewhere as a comment. The same terminology
> > applies to VLV as well.
> =

> Haven't seen the promised patch yet.

"[PATCH] drm/i915: Add a brief description of the VLV display PHY internals=
" & co.

-- =

Ville Syrj=E4l=E4
Intel OTC