* [PATCH] drm/i915: Add a brief description of the VLV display PHY internals @ 2014-04-25 13:32 ville.syrjala 2014-04-25 14:01 ` Daniel Vetter 0 siblings, 1 reply; 16+ messages in thread From: ville.syrjala @ 2014-04-25 13:32 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Document the internal structure of the VLV display PHY a bit to help people understand how the different register blocks relate to each other. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 40 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0eff337..064e599 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -571,7 +571,45 @@ enum punit_power_well { * * DPIO is VLV only. * - * Note: digital port B is DDI0, digital pot C is DDI1 + * Note: digital port B is DDI0, digital port C is DDI1 + * + * Each display PHY is made up of one or two channels. Each channel + * houses a common lane part which contains the PLL and other common + * logic. CH0 common lane also contains the IOSF-SB logic for the + * Common Register Interface (CRI) ie. the DPIO registers. CRI clock + * must be running when any DPIO registers are accessed. + * + * Eeach channel also has two splines, and each spline is made up of + * one Physical Access Coding Sub-Layer (PCS) block and two TX lanes. + * So each channel has two PCS blocks and four TX lanes. The TX lanes + * are used as DP lanes or TMDS data/clock pairs depending on the + * output type. + * + * Additionally the PHY also contains an AUX lane with AUX blocks + * for each channel. This is used for DP AUX communication, but + * this fact isn't really relevant for the driver since AUX is + * controlled from the display controller side. No DPIO registers + * need to be accessed during AUX communication, + * + * Generally the common lane corresponds to the pipe and + * the spline (PCS/TX) correponds to the port: + * pipe A == CMN/PLL/REF CH0 + * pipe B == CMN/PLL/REF CH1 + * port B == PCS/TX CH0 + * port C == PCS/TX CH1 + * This is especially important when we cross the streams + * ie. drive port B with pipe B, or port C with pipe A. + * + * --------------------------------- + * | CH0 | CH1 | + * | CMN/PLL/REF | CMN/PLL/REF | + * |---------------|---------------| Display PHY + * | PCS01 | PCS23 | PCS01 | PCS23 | + * |-------|-------|-------|-------| + * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| + * --------------------------------- + * | DDI0 | DDI1 | DP/HDMI ports + * --------------------------------- */ #define DPIO_DEVFN 0 #define DPIO_OPCODE_REG_WRITE 1 -- 1.8.3.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/i915: Add a brief description of the VLV display PHY internals 2014-04-25 13:32 [PATCH] drm/i915: Add a brief description of the VLV display PHY internals ville.syrjala @ 2014-04-25 14:01 ` Daniel Vetter 2014-04-25 14:01 ` Daniel Vetter 2014-04-25 17:14 ` [PATCH 1/3] drm/i915: Drop /** */ comments from i915_reg.h ville.syrjala 0 siblings, 2 replies; 16+ messages in thread From: Daniel Vetter @ 2014-04-25 14:01 UTC (permalink / raw) To: Syrjala, Ville; +Cc: intel-gfx On Fri, Apr 25, 2014 at 3:32 PM, <ville.syrjala@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Document the internal structure of the VLV display PHY a bit to help > people understand how the different register blocks relate to each > other. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Can you please make this into a kerneldoc DOC: comment and pull it into the i915 section of the drm reference docs? See e.g. how I've done the integration for drm_mm.c Cheers, Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/i915: Add a brief description of the VLV display PHY internals 2014-04-25 14:01 ` Daniel Vetter @ 2014-04-25 14:01 ` Daniel Vetter 2014-04-25 17:14 ` [PATCH 1/3] drm/i915: Drop /** */ comments from i915_reg.h ville.syrjala 1 sibling, 0 replies; 16+ messages in thread From: Daniel Vetter @ 2014-04-25 14:01 UTC (permalink / raw) To: Syrjala, Ville; +Cc: intel-gfx On Fri, Apr 25, 2014 at 4:01 PM, Daniel Vetter <daniel@ffwll.ch> wrote: > On Fri, Apr 25, 2014 at 3:32 PM, <ville.syrjala@linux.intel.com> wrote: >> From: Ville Syrjälä <ville.syrjala@linux.intel.com> >> >> Document the internal structure of the VLV display PHY a bit to help >> people understand how the different register blocks relate to each >> other. >> >> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Can you please make this into a kerneldoc DOC: comment and pull it > into the i915 section of the drm reference docs? See e.g. how I've > done the integration for drm_mm.c kerneldoc will wreak utter havoc with your table for the DocBook, but imo we can ignore that for now ... -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/3] drm/i915: Drop /** */ comments from i915_reg.h 2014-04-25 14:01 ` Daniel Vetter 2014-04-25 14:01 ` Daniel Vetter @ 2014-04-25 17:14 ` ville.syrjala 2014-04-25 17:14 ` [PATCH v2 2/3] drm/i915: Add a brief description of the VLV display PHY internals ville.syrjala ` (2 more replies) 1 sibling, 3 replies; 16+ messages in thread From: ville.syrjala @ 2014-04-25 17:14 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> The comments in i915_reg.h aren't proper kernel-doc comments, so replace the magic /** with just /* Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 246 ++++++++++++++++++++-------------------- 1 file changed, 123 insertions(+), 123 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0eff337..b6d5045 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1516,7 +1516,7 @@ enum punit_power_well { # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) -/** +/* * This bit must be set on the 830 to prevent hangs when turning off the * overlay scaler. */ @@ -1536,12 +1536,12 @@ enum punit_power_well { # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) # define MAG_CLOCK_GATE_DISABLE (1 << 5) -/** This bit must be unset on 855,865 */ +/* This bit must be unset on 855,865 */ # define MECI_CLOCK_GATE_DISABLE (1 << 4) # define DCMP_CLOCK_GATE_DISABLE (1 << 3) # define MEC_CLOCK_GATE_DISABLE (1 << 2) # define MECO_CLOCK_GATE_DISABLE (1 << 1) -/** This bit must be set on 855,865. */ +/* This bit must be set on 855,865. */ # define SV_CLOCK_GATE_DISABLE (1 << 0) # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) @@ -1562,14 +1562,14 @@ enum punit_power_well { # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) -/** This bit must always be set on 965G/965GM */ +/* This bit must always be set on 965G/965GM */ # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) -/** This bit must always be set on 965G */ +/* This bit must always be set on 965G */ # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) @@ -1635,7 +1635,7 @@ enum punit_power_well { /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ #define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04) -/** 915-945 and GM965 MCH register controlling DRAM channel access */ +/* 915-945 and GM965 MCH register controlling DRAM channel access */ #define DCC 0x10200 #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) @@ -1644,15 +1644,15 @@ enum punit_power_well { #define DCC_CHANNEL_XOR_DISABLE (1 << 10) #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) -/** Pineview MCH register contains DDR3 setting */ +/* Pineview MCH register contains DDR3 setting */ #define CSHRDDR3CTL 0x101a8 #define CSHRDDR3CTL_DDR3 (1 << 2) -/** 965 MCH register controlling DRAM channel configuration */ +/* 965 MCH register controlling DRAM channel configuration */ #define C0DRB3 0x10206 #define C1DRB3 0x10606 -/** snb MCH registers for reading the DRAM channel configuration */ +/* snb MCH registers for reading the DRAM channel configuration */ #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004) #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008) #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C) @@ -1674,7 +1674,7 @@ enum punit_power_well { #define MAD_DIMM_A_SIZE_SHIFT 0 #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) -/** snb MCH registers for priority tuning */ +/* snb MCH registers for priority tuning */ #define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10) #define MCH_SSKPD_WM0_MASK 0x3f #define MCH_SSKPD_WM0_VAL 0xc @@ -2346,7 +2346,7 @@ enum punit_power_well { #define SDVO_PIPE_B_SELECT (1 << 30) #define SDVO_STALL_SELECT (1 << 29) #define SDVO_INTERRUPT_ENABLE (1 << 26) -/** +/* * 915G/GM SDVO pixel multiplier. * Programmed value is multiplier - 1, up to 5x. * \sa DPLL_MD_UDI_MULTIPLIER_MASK @@ -2656,65 +2656,65 @@ enum punit_power_well { /* TV port control */ #define TV_CTL 0x68000 -/** Enables the TV encoder */ +/* Enables the TV encoder */ # define TV_ENC_ENABLE (1 << 31) -/** Sources the TV encoder input from pipe B instead of A. */ +/* Sources the TV encoder input from pipe B instead of A. */ # define TV_ENC_PIPEB_SELECT (1 << 30) -/** Outputs composite video (DAC A only) */ +/* Outputs composite video (DAC A only) */ # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) -/** Outputs SVideo video (DAC B/C) */ +/* Outputs SVideo video (DAC B/C) */ # define TV_ENC_OUTPUT_SVIDEO (1 << 28) -/** Outputs Component video (DAC A/B/C) */ +/* Outputs Component video (DAC A/B/C) */ # define TV_ENC_OUTPUT_COMPONENT (2 << 28) -/** Outputs Composite and SVideo (DAC A/B/C) */ +/* Outputs Composite and SVideo (DAC A/B/C) */ # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) # define TV_TRILEVEL_SYNC (1 << 21) -/** Enables slow sync generation (945GM only) */ +/* Enables slow sync generation (945GM only) */ # define TV_SLOW_SYNC (1 << 20) -/** Selects 4x oversampling for 480i and 576p */ +/* Selects 4x oversampling for 480i and 576p */ # define TV_OVERSAMPLE_4X (0 << 18) -/** Selects 2x oversampling for 720p and 1080i */ +/* Selects 2x oversampling for 720p and 1080i */ # define TV_OVERSAMPLE_2X (1 << 18) -/** Selects no oversampling for 1080p */ +/* Selects no oversampling for 1080p */ # define TV_OVERSAMPLE_NONE (2 << 18) -/** Selects 8x oversampling */ +/* Selects 8x oversampling */ # define TV_OVERSAMPLE_8X (3 << 18) -/** Selects progressive mode rather than interlaced */ +/* Selects progressive mode rather than interlaced */ # define TV_PROGRESSIVE (1 << 17) -/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ +/* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ # define TV_PAL_BURST (1 << 16) -/** Field for setting delay of Y compared to C */ +/* Field for setting delay of Y compared to C */ # define TV_YC_SKEW_MASK (7 << 12) -/** Enables a fix for 480p/576p standard definition modes on the 915GM only */ +/* Enables a fix for 480p/576p standard definition modes on the 915GM only */ # define TV_ENC_SDP_FIX (1 << 11) -/** +/* * Enables a fix for the 915GM only. * * Not sure what it does. */ # define TV_ENC_C0_FIX (1 << 10) -/** Bits that must be preserved by software */ +/* Bits that must be preserved by software */ # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) # define TV_FUSE_STATE_MASK (3 << 4) -/** Read-only state that reports all features enabled */ +/* Read-only state that reports all features enabled */ # define TV_FUSE_STATE_ENABLED (0 << 4) -/** Read-only state that reports that Macrovision is disabled in hardware*/ +/* Read-only state that reports that Macrovision is disabled in hardware*/ # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) -/** Read-only state that reports that TV-out is disabled in hardware. */ +/* Read-only state that reports that TV-out is disabled in hardware. */ # define TV_FUSE_STATE_DISABLED (2 << 4) -/** Normal operation */ +/* Normal operation */ # define TV_TEST_MODE_NORMAL (0 << 0) -/** Encoder test pattern 1 - combo pattern */ +/* Encoder test pattern 1 - combo pattern */ # define TV_TEST_MODE_PATTERN_1 (1 << 0) -/** Encoder test pattern 2 - full screen vertical 75% color bars */ +/* Encoder test pattern 2 - full screen vertical 75% color bars */ # define TV_TEST_MODE_PATTERN_2 (2 << 0) -/** Encoder test pattern 3 - full screen horizontal 75% color bars */ +/* Encoder test pattern 3 - full screen horizontal 75% color bars */ # define TV_TEST_MODE_PATTERN_3 (3 << 0) -/** Encoder test pattern 4 - random noise */ +/* Encoder test pattern 4 - random noise */ # define TV_TEST_MODE_PATTERN_4 (4 << 0) -/** Encoder test pattern 5 - linear color ramps */ +/* Encoder test pattern 5 - linear color ramps */ # define TV_TEST_MODE_PATTERN_5 (5 << 0) -/** +/* * This test mode forces the DACs to 50% of full output. * * This is used for load detection in combination with TVDAC_SENSE_MASK @@ -2724,35 +2724,35 @@ enum punit_power_well { #define TV_DAC 0x68004 # define TV_DAC_SAVE 0x00ffff00 -/** +/* * Reports that DAC state change logic has reported change (RO). * * This gets cleared when TV_DAC_STATE_EN is cleared */ # define TVDAC_STATE_CHG (1 << 31) # define TVDAC_SENSE_MASK (7 << 28) -/** Reports that DAC A voltage is above the detect threshold */ +/* Reports that DAC A voltage is above the detect threshold */ # define TVDAC_A_SENSE (1 << 30) -/** Reports that DAC B voltage is above the detect threshold */ +/* Reports that DAC B voltage is above the detect threshold */ # define TVDAC_B_SENSE (1 << 29) -/** Reports that DAC C voltage is above the detect threshold */ +/* Reports that DAC C voltage is above the detect threshold */ # define TVDAC_C_SENSE (1 << 28) -/** +/* * Enables DAC state detection logic, for load-based TV detection. * * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set * to off, for load detection to work. */ # define TVDAC_STATE_CHG_EN (1 << 27) -/** Sets the DAC A sense value to high */ +/* Sets the DAC A sense value to high */ # define TVDAC_A_SENSE_CTL (1 << 26) -/** Sets the DAC B sense value to high */ +/* Sets the DAC B sense value to high */ # define TVDAC_B_SENSE_CTL (1 << 25) -/** Sets the DAC C sense value to high */ +/* Sets the DAC C sense value to high */ # define TVDAC_C_SENSE_CTL (1 << 24) -/** Overrides the ENC_ENABLE and DAC voltage levels */ +/* Overrides the ENC_ENABLE and DAC voltage levels */ # define DAC_CTL_OVERRIDE (1 << 7) -/** Sets the slew rate. Must be preserved in software */ +/* Sets the slew rate. Must be preserved in software */ # define ENC_TVDAC_SLEW_FAST (1 << 6) # define DAC_A_1_3_V (0 << 4) # define DAC_A_1_1_V (1 << 4) @@ -2767,7 +2767,7 @@ enum punit_power_well { # define DAC_C_0_7_V (2 << 0) # define DAC_C_MASK (3 << 0) -/** +/* * CSC coefficients are stored in a floating point format with 9 bits of * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with @@ -2782,7 +2782,7 @@ enum punit_power_well { #define TV_CSC_Y2 0x68014 # define TV_BY_MASK 0x07ff0000 # define TV_BY_SHIFT 16 -/** +/* * Y attenuation for component video. * * Stored in 1.9 fixed point. @@ -2799,7 +2799,7 @@ enum punit_power_well { #define TV_CSC_U2 0x6801c # define TV_BU_MASK 0x07ff0000 # define TV_BU_SHIFT 16 -/** +/* * U attenuation for component video. * * Stored in 1.9 fixed point. @@ -2816,7 +2816,7 @@ enum punit_power_well { #define TV_CSC_V2 0x68024 # define TV_BV_MASK 0x07ff0000 # define TV_BV_SHIFT 16 -/** +/* * V attenuation for component video. * * Stored in 1.9 fixed point. @@ -2825,74 +2825,74 @@ enum punit_power_well { # define TV_AV_SHIFT 0 #define TV_CLR_KNOBS 0x68028 -/** 2s-complement brightness adjustment */ +/* 2s-complement brightness adjustment */ # define TV_BRIGHTNESS_MASK 0xff000000 # define TV_BRIGHTNESS_SHIFT 24 -/** Contrast adjustment, as a 2.6 unsigned floating point number */ +/* Contrast adjustment, as a 2.6 unsigned floating point number */ # define TV_CONTRAST_MASK 0x00ff0000 # define TV_CONTRAST_SHIFT 16 -/** Saturation adjustment, as a 2.6 unsigned floating point number */ +/* Saturation adjustment, as a 2.6 unsigned floating point number */ # define TV_SATURATION_MASK 0x0000ff00 # define TV_SATURATION_SHIFT 8 -/** Hue adjustment, as an integer phase angle in degrees */ +/* Hue adjustment, as an integer phase angle in degrees */ # define TV_HUE_MASK 0x000000ff # define TV_HUE_SHIFT 0 #define TV_CLR_LEVEL 0x6802c -/** Controls the DAC level for black */ +/* Controls the DAC level for black */ # define TV_BLACK_LEVEL_MASK 0x01ff0000 # define TV_BLACK_LEVEL_SHIFT 16 -/** Controls the DAC level for blanking */ +/* Controls the DAC level for blanking */ # define TV_BLANK_LEVEL_MASK 0x000001ff # define TV_BLANK_LEVEL_SHIFT 0 #define TV_H_CTL_1 0x68030 -/** Number of pixels in the hsync. */ +/* Number of pixels in the hsync. */ # define TV_HSYNC_END_MASK 0x1fff0000 # define TV_HSYNC_END_SHIFT 16 -/** Total number of pixels minus one in the line (display and blanking). */ +/* Total number of pixels minus one in the line (display and blanking). */ # define TV_HTOTAL_MASK 0x00001fff # define TV_HTOTAL_SHIFT 0 #define TV_H_CTL_2 0x68034 -/** Enables the colorburst (needed for non-component color) */ +/* Enables the colorburst (needed for non-component color) */ # define TV_BURST_ENA (1 << 31) -/** Offset of the colorburst from the start of hsync, in pixels minus one. */ +/* Offset of the colorburst from the start of hsync, in pixels minus one. */ # define TV_HBURST_START_SHIFT 16 # define TV_HBURST_START_MASK 0x1fff0000 -/** Length of the colorburst */ +/* Length of the colorburst */ # define TV_HBURST_LEN_SHIFT 0 # define TV_HBURST_LEN_MASK 0x0001fff #define TV_H_CTL_3 0x68038 -/** End of hblank, measured in pixels minus one from start of hsync */ +/* End of hblank, measured in pixels minus one from start of hsync */ # define TV_HBLANK_END_SHIFT 16 # define TV_HBLANK_END_MASK 0x1fff0000 -/** Start of hblank, measured in pixels minus one from start of hsync */ +/* Start of hblank, measured in pixels minus one from start of hsync */ # define TV_HBLANK_START_SHIFT 0 # define TV_HBLANK_START_MASK 0x0001fff #define TV_V_CTL_1 0x6803c -/** XXX */ +/* XXX */ # define TV_NBR_END_SHIFT 16 # define TV_NBR_END_MASK 0x07ff0000 -/** XXX */ +/* XXX */ # define TV_VI_END_F1_SHIFT 8 # define TV_VI_END_F1_MASK 0x00003f00 -/** XXX */ +/* XXX */ # define TV_VI_END_F2_SHIFT 0 # define TV_VI_END_F2_MASK 0x0000003f #define TV_V_CTL_2 0x68040 -/** Length of vsync, in half lines */ +/* Length of vsync, in half lines */ # define TV_VSYNC_LEN_MASK 0x07ff0000 # define TV_VSYNC_LEN_SHIFT 16 -/** Offset of the start of vsync in field 1, measured in one less than the +/* Offset of the start of vsync in field 1, measured in one less than the * number of half lines. */ # define TV_VSYNC_START_F1_MASK 0x00007f00 # define TV_VSYNC_START_F1_SHIFT 8 -/** +/* * Offset of the start of vsync in field 2, measured in one less than the * number of half lines. */ @@ -2900,17 +2900,17 @@ enum punit_power_well { # define TV_VSYNC_START_F2_SHIFT 0 #define TV_V_CTL_3 0x68044 -/** Enables generation of the equalization signal */ +/* Enables generation of the equalization signal */ # define TV_EQUAL_ENA (1 << 31) -/** Length of vsync, in half lines */ +/* Length of vsync, in half lines */ # define TV_VEQ_LEN_MASK 0x007f0000 # define TV_VEQ_LEN_SHIFT 16 -/** Offset of the start of equalization in field 1, measured in one less than +/* Offset of the start of equalization in field 1, measured in one less than * the number of half lines. */ # define TV_VEQ_START_F1_MASK 0x0007f00 # define TV_VEQ_START_F1_SHIFT 8 -/** +/* * Offset of the start of equalization in field 2, measured in one less than * the number of half lines. */ @@ -2918,13 +2918,13 @@ enum punit_power_well { # define TV_VEQ_START_F2_SHIFT 0 #define TV_V_CTL_4 0x68048 -/** +/* * Offset to start of vertical colorburst, measured in one less than the * number of lines from vertical start. */ # define TV_VBURST_START_F1_MASK 0x003f0000 # define TV_VBURST_START_F1_SHIFT 16 -/** +/* * Offset to the end of vertical colorburst, measured in one less than the * number of lines from the start of NBR. */ @@ -2932,13 +2932,13 @@ enum punit_power_well { # define TV_VBURST_END_F1_SHIFT 0 #define TV_V_CTL_5 0x6804c -/** +/* * Offset to start of vertical colorburst, measured in one less than the * number of lines from vertical start. */ # define TV_VBURST_START_F2_MASK 0x003f0000 # define TV_VBURST_START_F2_SHIFT 16 -/** +/* * Offset to the end of vertical colorburst, measured in one less than the * number of lines from the start of NBR. */ @@ -2946,13 +2946,13 @@ enum punit_power_well { # define TV_VBURST_END_F2_SHIFT 0 #define TV_V_CTL_6 0x68050 -/** +/* * Offset to start of vertical colorburst, measured in one less than the * number of lines from vertical start. */ # define TV_VBURST_START_F3_MASK 0x003f0000 # define TV_VBURST_START_F3_SHIFT 16 -/** +/* * Offset to the end of vertical colorburst, measured in one less than the * number of lines from the start of NBR. */ @@ -2960,13 +2960,13 @@ enum punit_power_well { # define TV_VBURST_END_F3_SHIFT 0 #define TV_V_CTL_7 0x68054 -/** +/* * Offset to start of vertical colorburst, measured in one less than the * number of lines from vertical start. */ # define TV_VBURST_START_F4_MASK 0x003f0000 # define TV_VBURST_START_F4_SHIFT 16 -/** +/* * Offset to the end of vertical colorburst, measured in one less than the * number of lines from the start of NBR. */ @@ -2974,56 +2974,56 @@ enum punit_power_well { # define TV_VBURST_END_F4_SHIFT 0 #define TV_SC_CTL_1 0x68060 -/** Turns on the first subcarrier phase generation DDA */ +/* Turns on the first subcarrier phase generation DDA */ # define TV_SC_DDA1_EN (1 << 31) -/** Turns on the first subcarrier phase generation DDA */ +/* Turns on the first subcarrier phase generation DDA */ # define TV_SC_DDA2_EN (1 << 30) -/** Turns on the first subcarrier phase generation DDA */ +/* Turns on the first subcarrier phase generation DDA */ # define TV_SC_DDA3_EN (1 << 29) -/** Sets the subcarrier DDA to reset frequency every other field */ +/* Sets the subcarrier DDA to reset frequency every other field */ # define TV_SC_RESET_EVERY_2 (0 << 24) -/** Sets the subcarrier DDA to reset frequency every fourth field */ +/* Sets the subcarrier DDA to reset frequency every fourth field */ # define TV_SC_RESET_EVERY_4 (1 << 24) -/** Sets the subcarrier DDA to reset frequency every eighth field */ +/* Sets the subcarrier DDA to reset frequency every eighth field */ # define TV_SC_RESET_EVERY_8 (2 << 24) -/** Sets the subcarrier DDA to never reset the frequency */ +/* Sets the subcarrier DDA to never reset the frequency */ # define TV_SC_RESET_NEVER (3 << 24) -/** Sets the peak amplitude of the colorburst.*/ +/* Sets the peak amplitude of the colorburst.*/ # define TV_BURST_LEVEL_MASK 0x00ff0000 # define TV_BURST_LEVEL_SHIFT 16 -/** Sets the increment of the first subcarrier phase generation DDA */ +/* Sets the increment of the first subcarrier phase generation DDA */ # define TV_SCDDA1_INC_MASK 0x00000fff # define TV_SCDDA1_INC_SHIFT 0 #define TV_SC_CTL_2 0x68064 -/** Sets the rollover for the second subcarrier phase generation DDA */ +/* Sets the rollover for the second subcarrier phase generation DDA */ # define TV_SCDDA2_SIZE_MASK 0x7fff0000 # define TV_SCDDA2_SIZE_SHIFT 16 -/** Sets the increent of the second subcarrier phase generation DDA */ +/* Sets the increent of the second subcarrier phase generation DDA */ # define TV_SCDDA2_INC_MASK 0x00007fff # define TV_SCDDA2_INC_SHIFT 0 #define TV_SC_CTL_3 0x68068 -/** Sets the rollover for the third subcarrier phase generation DDA */ +/* Sets the rollover for the third subcarrier phase generation DDA */ # define TV_SCDDA3_SIZE_MASK 0x7fff0000 # define TV_SCDDA3_SIZE_SHIFT 16 -/** Sets the increent of the third subcarrier phase generation DDA */ +/* Sets the increent of the third subcarrier phase generation DDA */ # define TV_SCDDA3_INC_MASK 0x00007fff # define TV_SCDDA3_INC_SHIFT 0 #define TV_WIN_POS 0x68070 -/** X coordinate of the display from the start of horizontal active */ +/* X coordinate of the display from the start of horizontal active */ # define TV_XPOS_MASK 0x1fff0000 # define TV_XPOS_SHIFT 16 -/** Y coordinate of the display from the start of vertical active (NBR) */ +/* Y coordinate of the display from the start of vertical active (NBR) */ # define TV_YPOS_MASK 0x00000fff # define TV_YPOS_SHIFT 0 #define TV_WIN_SIZE 0x68074 -/** Horizontal size of the display window, measured in pixels*/ +/* Horizontal size of the display window, measured in pixels*/ # define TV_XSIZE_MASK 0x1fff0000 # define TV_XSIZE_SHIFT 16 -/** +/* * Vertical size of the display window, measured in pixels. * * Must be even for interlaced modes. @@ -3032,28 +3032,28 @@ enum punit_power_well { # define TV_YSIZE_SHIFT 0 #define TV_FILTER_CTL_1 0x68080 -/** +/* * Enables automatic scaling calculation. * * If set, the rest of the registers are ignored, and the calculated values can * be read back from the register. */ # define TV_AUTO_SCALE (1 << 31) -/** +/* * Disables the vertical filter. * * This is required on modes more than 1024 pixels wide */ # define TV_V_FILTER_BYPASS (1 << 29) -/** Enables adaptive vertical filtering */ +/* Enables adaptive vertical filtering */ # define TV_VADAPT (1 << 28) # define TV_VADAPT_MODE_MASK (3 << 26) -/** Selects the least adaptive vertical filtering mode */ +/* Selects the least adaptive vertical filtering mode */ # define TV_VADAPT_MODE_LEAST (0 << 26) -/** Selects the moderately adaptive vertical filtering mode */ +/* Selects the moderately adaptive vertical filtering mode */ # define TV_VADAPT_MODE_MODERATE (1 << 26) -/** Selects the most adaptive vertical filtering mode */ +/* Selects the most adaptive vertical filtering mode */ # define TV_VADAPT_MODE_MOST (3 << 26) -/** +/* * Sets the horizontal scaling factor. * * This should be the fractional part of the horizontal scaling factor divided @@ -3065,14 +3065,14 @@ enum punit_power_well { # define TV_HSCALE_FRAC_SHIFT 0 #define TV_FILTER_CTL_2 0x68084 -/** +/* * Sets the integer part of the 3.15 fixed-point vertical scaling factor. * * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) */ # define TV_VSCALE_INT_MASK 0x00038000 # define TV_VSCALE_INT_SHIFT 15 -/** +/* * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. * * \sa TV_VSCALE_INT_MASK @@ -3081,7 +3081,7 @@ enum punit_power_well { # define TV_VSCALE_FRAC_SHIFT 0 #define TV_FILTER_CTL_3 0x68088 -/** +/* * Sets the integer part of the 3.15 fixed-point vertical scaling factor. * * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) @@ -3090,7 +3090,7 @@ enum punit_power_well { */ # define TV_VSCALE_IP_INT_MASK 0x00038000 # define TV_VSCALE_IP_INT_SHIFT 15 -/** +/* * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. * * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. @@ -3102,26 +3102,26 @@ enum punit_power_well { #define TV_CC_CONTROL 0x68090 # define TV_CC_ENABLE (1 << 31) -/** +/* * Specifies which field to send the CC data in. * * CC data is usually sent in field 0. */ # define TV_CC_FID_MASK (1 << 27) # define TV_CC_FID_SHIFT 27 -/** Sets the horizontal position of the CC data. Usually 135. */ +/* Sets the horizontal position of the CC data. Usually 135. */ # define TV_CC_HOFF_MASK 0x03ff0000 # define TV_CC_HOFF_SHIFT 16 -/** Sets the vertical position of the CC data. Usually 21 */ +/* Sets the vertical position of the CC data. Usually 21 */ # define TV_CC_LINE_MASK 0x0000003f # define TV_CC_LINE_SHIFT 0 #define TV_CC_DATA 0x68094 # define TV_CC_RDY (1 << 31) -/** Second word of CC data to be transmitted. */ +/* Second word of CC data to be transmitted. */ # define TV_CC_DATA_2_MASK 0x007f0000 # define TV_CC_DATA_2_SHIFT 16 -/** First word of CC data to be transmitted. */ +/* First word of CC data to be transmitted. */ # define TV_CC_DATA_1_MASK 0x0000007f # define TV_CC_DATA_1_SHIFT 0 @@ -3190,32 +3190,32 @@ enum punit_power_well { #define DP_PLL_FREQ_160MHZ (1 << 16) #define DP_PLL_FREQ_MASK (3 << 16) -/** locked once port is enabled */ +/* locked once port is enabled */ #define DP_PORT_REVERSAL (1 << 15) /* eDP */ #define DP_PLL_ENABLE (1 << 14) -/** sends the clock on lane 15 of the PEG for debug */ +/* sends the clock on lane 15 of the PEG for debug */ #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) #define DP_SCRAMBLING_DISABLE (1 << 12) #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) -/** limit RGB values to avoid confusing TVs */ +/* limit RGB values to avoid confusing TVs */ #define DP_COLOR_RANGE_16_235 (1 << 8) -/** Turn on the audio link */ +/* Turn on the audio link */ #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) -/** vs and hs sync polarity */ +/* vs and hs sync polarity */ #define DP_SYNC_VS_HIGH (1 << 4) #define DP_SYNC_HS_HIGH (1 << 3) -/** A fantasy */ +/* A fantasy */ #define DP_DETECTED (1 << 2) -/** The aux channel provides a way to talk to the +/* The aux channel provides a way to talk to the * signal sink for DDC etc. Max packet size supported * is 20 bytes in each direction, hence the 5 fixed * data registers -- 1.8.3.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 2/3] drm/i915: Add a brief description of the VLV display PHY internals 2014-04-25 17:14 ` [PATCH 1/3] drm/i915: Drop /** */ comments from i915_reg.h ville.syrjala @ 2014-04-25 17:14 ` ville.syrjala 2014-04-25 17:44 ` Daniel Vetter 2014-05-21 8:31 ` Lee, Chon Ming 2014-04-25 17:14 ` [PATCH 3/3] drm/i915: Provide DPIO diagrams as docboox tables ville.syrjala 2014-05-20 14:13 ` [PATCH 1/3] drm/i915: Drop /** */ comments from i915_reg.h Damien Lespiau 2 siblings, 2 replies; 16+ messages in thread From: ville.syrjala @ 2014-04-25 17:14 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Document the internal structure of the VLV display PHY a bit to help people understand how the different register blocks relate to each other. v2: Add a bit more text Make it a DOC: comment, but leave the ascii art out since it would get mangled Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- Documentation/DocBook/drm.tmpl | 4 ++ drivers/gpu/drm/i915/i915_reg.h | 85 +++++++++++++++++++++++++++++++++++++++-- 2 files changed, 85 insertions(+), 4 deletions(-) diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl index 4a955b4..e361ccd 100644 --- a/Documentation/DocBook/drm.tmpl +++ b/Documentation/DocBook/drm.tmpl @@ -2942,6 +2942,10 @@ int num_ioctls;</synopsis> probing, so those sections fully apply. </para> </sect2> + <sect2> + <title>DPIO</title> +!Pdrivers/gpu/drm/i915/i915_reg.h DPIO + </sect2> </sect1> <sect1> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b6d5045..8e18e8f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -566,12 +566,89 @@ enum punit_power_well { #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) #define CCK_DISPLAY_CLOCK_CONTROL 0x6b -/* - * DPIO - a special bus for various display related registers to hide behind +/** + * DOC: DPIO + * + * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI + * ports. DPIO is the name given to such a display PHY. These PHYs + * don't follow the standard programming model using direct MMIO + * registers, and instead their registers must be accessed trough IOSF + * sideband. VLV has one such PHY for driving ports B and C, and CHV + * adds another PHY for driving port D. Each PHY responds to specific + * IOSF-SB port. + * + * Each display PHY is made up of one or two channels. Each channel + * houses a common lane part which contains the PLL and other common + * logic. CH0 common lane also contains the IOSF-SB logic for the + * Common Register Interface (CRI) ie. the DPIO registers. CRI clock + * must be running when any DPIO registers are accessed. + * + * In addition to having their own registers, the PHYs are also + * controlled through some dedicated signals from the display + * controller. These include PLL reference clock enable, PLL enable, + * and CRI clock selection, for example. + * + * Eeach channel also has two splines (also called data lanes), and + * each spline is made up of one Physical Access Coding Sub-Layer + * (PCS) block and two TX lanes. So each channel has two PCS blocks + * and four TX lanes. The TX lanes are used as DP lanes or TMDS + * data/clock pairs depending on the output type. + * + * Additionally the PHY also contains an AUX lane with AUX blocks + * for each channel. This is used for DP AUX communication, but + * this fact isn't really relevant for the driver since AUX is + * controlled from the display controller side. No DPIO registers + * need to be accessed during AUX communication, + * + * Generally the common lane corresponds to the pipe and + * the spline (PCS/TX) correponds to the port. + * + * For dual channel PHY (VLV/CHV): + * + * pipe A == CMN/PLL/REF CH0 * - * DPIO is VLV only. + * pipe B == CMN/PLL/REF CH1 + * + * port B == PCS/TX CH0 + * + * port C == PCS/TX CH1 + * + * This is especially important when we cross the streams + * ie. drive port B with pipe B, or port C with pipe A. + * + * For single channel PHY (CHV): + * + * pipe C == CMN/PLL/REF CH0 + * + * port D == PCS/TX CH0 + * + * Note: digital port B is DDI0, digital port C is DDI1, + * digital port D is DDI2 + */ +/* + * Dual channel PHY (VLV/CHV) + * --------------------------------- + * | CH0 | CH1 | + * | CMN/PLL/REF | CMN/PLL/REF | + * |---------------|---------------| Display PHY + * | PCS01 | PCS23 | PCS01 | PCS23 | + * |-------|-------|-------|-------| + * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| + * --------------------------------- + * | DDI0 | DDI1 | DP/HDMI ports + * --------------------------------- * - * Note: digital port B is DDI0, digital pot C is DDI1 + * Single channel PHY (CHV) + * ----------------- + * | CH0 | + * | CMN/PLL/REF | + * |---------------| Display PHY + * | PCS01 | PCS23 | + * |-------|-------| + * |TX0|TX1|TX2|TX3| + * ----------------- + * | DDI2 | DP/HDMI port + * ----------------- */ #define DPIO_DEVFN 0 #define DPIO_OPCODE_REG_WRITE 1 -- 1.8.3.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v2 2/3] drm/i915: Add a brief description of the VLV display PHY internals 2014-04-25 17:14 ` [PATCH v2 2/3] drm/i915: Add a brief description of the VLV display PHY internals ville.syrjala @ 2014-04-25 17:44 ` Daniel Vetter 2014-05-20 14:18 ` Daniel Vetter 2014-05-21 8:31 ` Lee, Chon Ming 1 sibling, 1 reply; 16+ messages in thread From: Daniel Vetter @ 2014-04-25 17:44 UTC (permalink / raw) To: Syrjala, Ville, Lee, Chon Ming; +Cc: intel-gfx On Fri, Apr 25, 2014 at 7:14 PM, <ville.syrjala@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Document the internal structure of the VLV display PHY a bit to help > people understand how the different register blocks relate to each > other. > > v2: Add a bit more text > Make it a DOC: comment, but leave the ascii art out since > it would get mangled > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Chon can you please review these documentation patches from Ville quickly? You've done all the chv phy enabling after all. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 2/3] drm/i915: Add a brief description of the VLV display PHY internals 2014-04-25 17:44 ` Daniel Vetter @ 2014-05-20 14:18 ` Daniel Vetter 0 siblings, 0 replies; 16+ messages in thread From: Daniel Vetter @ 2014-05-20 14:18 UTC (permalink / raw) To: Syrjala, Ville, Lee, Chon Ming; +Cc: intel-gfx On Fri, Apr 25, 2014 at 7:44 PM, Daniel Vetter <daniel@ffwll.ch> wrote: > On Fri, Apr 25, 2014 at 7:14 PM, <ville.syrjala@linux.intel.com> wrote: >> From: Ville Syrjälä <ville.syrjala@linux.intel.com> >> >> Document the internal structure of the VLV display PHY a bit to help >> people understand how the different register blocks relate to each >> other. >> >> v2: Add a bit more text >> Make it a DOC: comment, but leave the ascii art out since >> it would get mangled >> >> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Chon can you please review these documentation patches from Ville > quickly? You've done all the chv phy enabling after all. Ping for the review .... -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 2/3] drm/i915: Add a brief description of the VLV display PHY internals 2014-04-25 17:14 ` [PATCH v2 2/3] drm/i915: Add a brief description of the VLV display PHY internals ville.syrjala 2014-04-25 17:44 ` Daniel Vetter @ 2014-05-21 8:31 ` Lee, Chon Ming 2014-05-21 8:49 ` Ville Syrjälä 1 sibling, 1 reply; 16+ messages in thread From: Lee, Chon Ming @ 2014-05-21 8:31 UTC (permalink / raw) To: ville.syrjala; +Cc: intel-gfx On 04/25 20:14, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Document the internal structure of the VLV display PHY a bit to help > people understand how the different register blocks relate to each > other. > > v2: Add a bit more text > Make it a DOC: comment, but leave the ascii art out since > it would get mangled > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > Documentation/DocBook/drm.tmpl | 4 ++ > drivers/gpu/drm/i915/i915_reg.h | 85 +++++++++++++++++++++++++++++++++++++++-- > 2 files changed, 85 insertions(+), 4 deletions(-) > > diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl > index 4a955b4..e361ccd 100644 > --- a/Documentation/DocBook/drm.tmpl > +++ b/Documentation/DocBook/drm.tmpl > @@ -2942,6 +2942,10 @@ int num_ioctls;</synopsis> > probing, so those sections fully apply. > </para> > </sect2> > + <sect2> > + <title>DPIO</title> > +!Pdrivers/gpu/drm/i915/i915_reg.h DPIO > + </sect2> > </sect1> > > <sect1> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index b6d5045..8e18e8f 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -566,12 +566,89 @@ enum punit_power_well { > #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) > #define CCK_DISPLAY_CLOCK_CONTROL 0x6b > > -/* > - * DPIO - a special bus for various display related registers to hide behind > +/** > + * DOC: DPIO > + * > + * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI > + * ports. DPIO is the name given to such a display PHY. These PHYs > + * don't follow the standard programming model using direct MMIO > + * registers, and instead their registers must be accessed trough IOSF > + * sideband. VLV has one such PHY for driving ports B and C, and CHV > + * adds another PHY for driving port D. Each PHY responds to specific > + * IOSF-SB port. > + * > + * Each display PHY is made up of one or two channels. Each channel > + * houses a common lane part which contains the PLL and other common > + * logic. CH0 common lane also contains the IOSF-SB logic for the > + * Common Register Interface (CRI) ie. the DPIO registers. CRI clock > + * must be running when any DPIO registers are accessed. > + * > + * In addition to having their own registers, the PHYs are also > + * controlled through some dedicated signals from the display > + * controller. These include PLL reference clock enable, PLL enable, > + * and CRI clock selection, for example. > + * > + * Eeach channel also has two splines (also called data lanes), and > + * each spline is made up of one Physical Access Coding Sub-Layer > + * (PCS) block and two TX lanes. So each channel has two PCS blocks > + * and four TX lanes. The TX lanes are used as DP lanes or TMDS > + * data/clock pairs depending on the output type. > + * > + * Additionally the PHY also contains an AUX lane with AUX blocks > + * for each channel. This is used for DP AUX communication, but > + * this fact isn't really relevant for the driver since AUX is > + * controlled from the display controller side. No DPIO registers > + * need to be accessed during AUX communication, > + * > + * Generally the common lane corresponds to the pipe and > + * the spline (PCS/TX) correponds to the port. > + * > + * For dual channel PHY (VLV/CHV): > + * > + * pipe A == CMN/PLL/REF CH0 > * > - * DPIO is VLV only. > + * pipe B == CMN/PLL/REF CH1 > + * > + * port B == PCS/TX CH0 > + * > + * port C == PCS/TX CH1 > + * > + * This is especially important when we cross the streams > + * ie. drive port B with pipe B, or port C with pipe A. > + * Do you want to add something like the PHY actually allow PLL CH0 to supply clock to both ports, same as PLL CH1. But this is something i915 not supported yet, for power saving purpose. > + * For single channel PHY (CHV): > + * > + * pipe C == CMN/PLL/REF CH0 > + * > + * port D == PCS/TX CH0 > + * > + * Note: digital port B is DDI0, digital port C is DDI1, > + * digital port D is DDI2 > + */ > +/* > + * Dual channel PHY (VLV/CHV) > + * --------------------------------- > + * | CH0 | CH1 | > + * | CMN/PLL/REF | CMN/PLL/REF | There is a AUX for both CH0 and CH1. Other than this, Reviewed-by: Chon Ming Lee <chon.ming.lee@intel.com> > + * |---------------|---------------| Display PHY > + * | PCS01 | PCS23 | PCS01 | PCS23 | > + * |-------|-------|-------|-------| > + * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| > + * --------------------------------- > + * | DDI0 | DDI1 | DP/HDMI ports > + * --------------------------------- > * > - * Note: digital port B is DDI0, digital pot C is DDI1 > + * Single channel PHY (CHV) > + * ----------------- > + * | CH0 | > + * | CMN/PLL/REF | > + * |---------------| Display PHY > + * | PCS01 | PCS23 | > + * |-------|-------| > + * |TX0|TX1|TX2|TX3| > + * ----------------- > + * | DDI2 | DP/HDMI port > + * ----------------- > */ > #define DPIO_DEVFN 0 > #define DPIO_OPCODE_REG_WRITE 1 > -- > 1.8.3.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 2/3] drm/i915: Add a brief description of the VLV display PHY internals 2014-05-21 8:31 ` Lee, Chon Ming @ 2014-05-21 8:49 ` Ville Syrjälä 2014-05-21 9:58 ` Lee, Chon Ming 0 siblings, 1 reply; 16+ messages in thread From: Ville Syrjälä @ 2014-05-21 8:49 UTC (permalink / raw) To: Lee, Chon Ming; +Cc: intel-gfx On Wed, May 21, 2014 at 04:31:37PM +0800, Lee, Chon Ming wrote: > On 04/25 20:14, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > Document the internal structure of the VLV display PHY a bit to help > > people understand how the different register blocks relate to each > > other. > > > > v2: Add a bit more text > > Make it a DOC: comment, but leave the ascii art out since > > it would get mangled > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > --- > > Documentation/DocBook/drm.tmpl | 4 ++ > > drivers/gpu/drm/i915/i915_reg.h | 85 +++++++++++++++++++++++++++++++++++++++-- > > 2 files changed, 85 insertions(+), 4 deletions(-) > > > > diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl > > index 4a955b4..e361ccd 100644 > > --- a/Documentation/DocBook/drm.tmpl > > +++ b/Documentation/DocBook/drm.tmpl > > @@ -2942,6 +2942,10 @@ int num_ioctls;</synopsis> > > probing, so those sections fully apply. > > </para> > > </sect2> > > + <sect2> > > + <title>DPIO</title> > > +!Pdrivers/gpu/drm/i915/i915_reg.h DPIO > > + </sect2> > > </sect1> > > > > <sect1> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index b6d5045..8e18e8f 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -566,12 +566,89 @@ enum punit_power_well { > > #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) > > #define CCK_DISPLAY_CLOCK_CONTROL 0x6b > > > > -/* > > - * DPIO - a special bus for various display related registers to hide behind > > +/** > > + * DOC: DPIO > > + * > > + * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI > > + * ports. DPIO is the name given to such a display PHY. These PHYs > > + * don't follow the standard programming model using direct MMIO > > + * registers, and instead their registers must be accessed trough IOSF > > + * sideband. VLV has one such PHY for driving ports B and C, and CHV > > + * adds another PHY for driving port D. Each PHY responds to specific > > + * IOSF-SB port. > > + * > > + * Each display PHY is made up of one or two channels. Each channel > > + * houses a common lane part which contains the PLL and other common > > + * logic. CH0 common lane also contains the IOSF-SB logic for the > > + * Common Register Interface (CRI) ie. the DPIO registers. CRI clock > > + * must be running when any DPIO registers are accessed. > > + * > > + * In addition to having their own registers, the PHYs are also > > + * controlled through some dedicated signals from the display > > + * controller. These include PLL reference clock enable, PLL enable, > > + * and CRI clock selection, for example. > > + * > > + * Eeach channel also has two splines (also called data lanes), and > > + * each spline is made up of one Physical Access Coding Sub-Layer > > + * (PCS) block and two TX lanes. So each channel has two PCS blocks > > + * and four TX lanes. The TX lanes are used as DP lanes or TMDS > > + * data/clock pairs depending on the output type. > > + * > > + * Additionally the PHY also contains an AUX lane with AUX blocks > > + * for each channel. This is used for DP AUX communication, but > > + * this fact isn't really relevant for the driver since AUX is > > + * controlled from the display controller side. No DPIO registers > > + * need to be accessed during AUX communication, > > + * > > + * Generally the common lane corresponds to the pipe and > > + * the spline (PCS/TX) correponds to the port. > > + * > > + * For dual channel PHY (VLV/CHV): > > + * > > + * pipe A == CMN/PLL/REF CH0 > > * > > - * DPIO is VLV only. > > + * pipe B == CMN/PLL/REF CH1 > > + * > > + * port B == PCS/TX CH0 > > + * > > + * port C == PCS/TX CH1 > > + * > > + * This is especially important when we cross the streams > > + * ie. drive port B with pipe B, or port C with pipe A. > > + * > > > Do you want to add something like the PHY actually allow PLL CH0 to supply clock > to both ports, same as PLL CH1. But this is something i915 not supported yet, > for power saving purpose. Maybe we can add the comment if and when we implement it. I'm not even sure if we should implement it since it might lead to blinking displays if we have to reroute the PLLs for active pipes. Although maybe it's possible to swap over to the pipe's own PLL from the shared case w/o blinking, but that would require special code in the modeset path since we'd need to make sure we fire up the new PLL first, then swap the PLLs, and only then can reprogram the old PLL. So unless the power savings are really significant I'm not sure anyone will bother with this. OTOH we already have potential display blinking due to the cdclk change logic, so maybe we don't care that much. > > > + * For single channel PHY (CHV): > > + * > > + * pipe C == CMN/PLL/REF CH0 > > + * > > + * port D == PCS/TX CH0 > > + * > > + * Note: digital port B is DDI0, digital port C is DDI1, > > + * digital port D is DDI2 > > + */ > > +/* > > + * Dual channel PHY (VLV/CHV) > > + * --------------------------------- > > + * | CH0 | CH1 | > > + * | CMN/PLL/REF | CMN/PLL/REF | > > There is a AUX for both CH0 and CH1. I left out AUX since the fact that it's part of the PHY isn't really significant for us. I did mention it in the text. > > Other than this, > > Reviewed-by: Chon Ming Lee <chon.ming.lee@intel.com> > > > > + * |---------------|---------------| Display PHY > > + * | PCS01 | PCS23 | PCS01 | PCS23 | > > + * |-------|-------|-------|-------| > > + * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| > > + * --------------------------------- > > + * | DDI0 | DDI1 | DP/HDMI ports > > + * --------------------------------- > > * > > - * Note: digital port B is DDI0, digital pot C is DDI1 > > + * Single channel PHY (CHV) > > + * ----------------- > > + * | CH0 | > > + * | CMN/PLL/REF | > > + * |---------------| Display PHY > > + * | PCS01 | PCS23 | > > + * |-------|-------| > > + * |TX0|TX1|TX2|TX3| > > + * ----------------- > > + * | DDI2 | DP/HDMI port > > + * ----------------- > > */ > > #define DPIO_DEVFN 0 > > #define DPIO_OPCODE_REG_WRITE 1 > > -- > > 1.8.3.2 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 2/3] drm/i915: Add a brief description of the VLV display PHY internals 2014-05-21 8:49 ` Ville Syrjälä @ 2014-05-21 9:58 ` Lee, Chon Ming 2014-05-21 10:31 ` Ville Syrjälä 0 siblings, 1 reply; 16+ messages in thread From: Lee, Chon Ming @ 2014-05-21 9:58 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx@lists.freedesktop.org > -----Original Message----- > From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com] > Sent: Wednesday, May 21, 2014 4:50 PM > To: Lee, Chon Ming > Cc: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Add a brief description of > the VLV display PHY internals > > On Wed, May 21, 2014 at 04:31:37PM +0800, Lee, Chon Ming wrote: > > On 04/25 20:14, ville.syrjala@linux.intel.com wrote: > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > > > Document the internal structure of the VLV display PHY a bit to help > > > people understand how the different register blocks relate to each > > > other. > > > > > > v2: Add a bit more text > > > Make it a DOC: comment, but leave the ascii art out since > > > it would get mangled > > > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > --- > > > Documentation/DocBook/drm.tmpl | 4 ++ > > > drivers/gpu/drm/i915/i915_reg.h | 85 > > > +++++++++++++++++++++++++++++++++++++++-- > > > 2 files changed, 85 insertions(+), 4 deletions(-) > > > > > > diff --git a/Documentation/DocBook/drm.tmpl > > > b/Documentation/DocBook/drm.tmpl index 4a955b4..e361ccd 100644 > > > --- a/Documentation/DocBook/drm.tmpl > > > +++ b/Documentation/DocBook/drm.tmpl > > > @@ -2942,6 +2942,10 @@ int num_ioctls;</synopsis> > > > probing, so those sections fully apply. > > > </para> > > > </sect2> > > > + <sect2> > > > + <title>DPIO</title> > > > +!Pdrivers/gpu/drm/i915/i915_reg.h DPIO > > > + </sect2> > > > </sect1> > > > > > > <sect1> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > > b/drivers/gpu/drm/i915/i915_reg.h index b6d5045..8e18e8f 100644 > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > @@ -566,12 +566,89 @@ enum punit_power_well { > > > #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) > > > #define CCK_DISPLAY_CLOCK_CONTROL 0x6b > > > > > > -/* > > > - * DPIO - a special bus for various display related registers to > > > hide behind > > > +/** This is something I miss out. The /** should be /* to match what you want to do in the first patch. Regards, Chon Ming > > > + * DOC: DPIO > > > + * > > > + * VLV and CHV have slightly peculiar display PHYs for driving > > > +DP/HDMI > > > + * ports. DPIO is the name given to such a display PHY. These PHYs > > > + * don't follow the standard programming model using direct MMIO > > > + * registers, and instead their registers must be accessed trough > > > +IOSF > > > + * sideband. VLV has one such PHY for driving ports B and C, and > > > +CHV > > > + * adds another PHY for driving port D. Each PHY responds to > > > +specific > > > + * IOSF-SB port. > > > + * > > > + * Each display PHY is made up of one or two channels. Each channel > > > + * houses a common lane part which contains the PLL and other > > > +common > > > + * logic. CH0 common lane also contains the IOSF-SB logic for the > > > + * Common Register Interface (CRI) ie. the DPIO registers. CRI > > > +clock > > > + * must be running when any DPIO registers are accessed. > > > + * > > > + * In addition to having their own registers, the PHYs are also > > > + * controlled through some dedicated signals from the display > > > + * controller. These include PLL reference clock enable, PLL > > > +enable, > > > + * and CRI clock selection, for example. > > > + * > > > + * Eeach channel also has two splines (also called data lanes), and > > > + * each spline is made up of one Physical Access Coding Sub-Layer > > > + * (PCS) block and two TX lanes. So each channel has two PCS blocks > > > + * and four TX lanes. The TX lanes are used as DP lanes or TMDS > > > + * data/clock pairs depending on the output type. > > > + * > > > + * Additionally the PHY also contains an AUX lane with AUX blocks > > > + * for each channel. This is used for DP AUX communication, but > > > + * this fact isn't really relevant for the driver since AUX is > > > + * controlled from the display controller side. No DPIO registers > > > + * need to be accessed during AUX communication, > > > + * > > > + * Generally the common lane corresponds to the pipe and > > > + * the spline (PCS/TX) correponds to the port. > > > + * > > > + * For dual channel PHY (VLV/CHV): > > > + * > > > + * pipe A == CMN/PLL/REF CH0 > > > * > > > - * DPIO is VLV only. > > > + * pipe B == CMN/PLL/REF CH1 > > > + * > > > + * port B == PCS/TX CH0 > > > + * > > > + * port C == PCS/TX CH1 > > > + * > > > + * This is especially important when we cross the streams > > > + * ie. drive port B with pipe B, or port C with pipe A. > > > + * > > > > > > Do you want to add something like the PHY actually allow PLL CH0 to > > supply clock to both ports, same as PLL CH1. But this is something > > i915 not supported yet, for power saving purpose. > > Maybe we can add the comment if and when we implement it. > > I'm not even sure if we should implement it since it might lead to blinking > displays if we have to reroute the PLLs for active pipes. > Although maybe it's possible to swap over to the pipe's own PLL from the > shared case w/o blinking, but that would require special code in the modeset > path since we'd need to make sure we fire up the new PLL first, then swap > the PLLs, and only then can reprogram the old PLL. > > So unless the power savings are really significant I'm not sure anyone will > bother with this. > > OTOH we already have potential display blinking due to the cdclk change logic, > so maybe we don't care that much. > > > > > > + * For single channel PHY (CHV): > > > + * > > > + * pipe C == CMN/PLL/REF CH0 > > > + * > > > + * port D == PCS/TX CH0 > > > + * > > > + * Note: digital port B is DDI0, digital port C is DDI1, > > > + * digital port D is DDI2 > > > + */ > > > +/* > > > + * Dual channel PHY (VLV/CHV) > > > + * --------------------------------- > > > + * | CH0 | CH1 | > > > + * | CMN/PLL/REF | CMN/PLL/REF | > > > > There is a AUX for both CH0 and CH1. > > I left out AUX since the fact that it's part of the PHY isn't really significant for > us. I did mention it in the text. > > > > > Other than this, > > > > Reviewed-by: Chon Ming Lee <chon.ming.lee@intel.com> > > > > > > > + * |---------------|---------------| Display PHY > > > + * | PCS01 | PCS23 | PCS01 | PCS23 | > > > + * |-------|-------|-------|-------| > > > + * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| > > > + * --------------------------------- > > > + * | DDI0 | DDI1 | DP/HDMI ports > > > + * --------------------------------- > > > * > > > - * Note: digital port B is DDI0, digital pot C is DDI1 > > > + * Single channel PHY (CHV) > > > + * ----------------- > > > + * | CH0 | > > > + * | CMN/PLL/REF | > > > + * |---------------| Display PHY > > > + * | PCS01 | PCS23 | > > > + * |-------|-------| > > > + * |TX0|TX1|TX2|TX3| > > > + * ----------------- > > > + * | DDI2 | DP/HDMI port > > > + * ----------------- > > > */ > > > #define DPIO_DEVFN 0 > > > #define DPIO_OPCODE_REG_WRITE 1 > > > -- > > > 1.8.3.2 > > > > > > _______________________________________________ > > > Intel-gfx mailing list > > > Intel-gfx@lists.freedesktop.org > > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrjälä > Intel OTC ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 2/3] drm/i915: Add a brief description of the VLV display PHY internals 2014-05-21 9:58 ` Lee, Chon Ming @ 2014-05-21 10:31 ` Ville Syrjälä 0 siblings, 0 replies; 16+ messages in thread From: Ville Syrjälä @ 2014-05-21 10:31 UTC (permalink / raw) To: Lee, Chon Ming; +Cc: intel-gfx@lists.freedesktop.org On Wed, May 21, 2014 at 09:58:35AM +0000, Lee, Chon Ming wrote: > > > > -----Original Message----- > > From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com] > > Sent: Wednesday, May 21, 2014 4:50 PM > > To: Lee, Chon Ming > > Cc: intel-gfx@lists.freedesktop.org > > Subject: Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Add a brief description of > > the VLV display PHY internals > > > > On Wed, May 21, 2014 at 04:31:37PM +0800, Lee, Chon Ming wrote: > > > On 04/25 20:14, ville.syrjala@linux.intel.com wrote: > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > > > > > Document the internal structure of the VLV display PHY a bit to help > > > > people understand how the different register blocks relate to each > > > > other. > > > > > > > > v2: Add a bit more text > > > > Make it a DOC: comment, but leave the ascii art out since > > > > it would get mangled > > > > > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > --- > > > > Documentation/DocBook/drm.tmpl | 4 ++ > > > > drivers/gpu/drm/i915/i915_reg.h | 85 > > > > +++++++++++++++++++++++++++++++++++++++-- > > > > 2 files changed, 85 insertions(+), 4 deletions(-) > > > > > > > > diff --git a/Documentation/DocBook/drm.tmpl > > > > b/Documentation/DocBook/drm.tmpl index 4a955b4..e361ccd 100644 > > > > --- a/Documentation/DocBook/drm.tmpl > > > > +++ b/Documentation/DocBook/drm.tmpl > > > > @@ -2942,6 +2942,10 @@ int num_ioctls;</synopsis> > > > > probing, so those sections fully apply. > > > > </para> > > > > </sect2> > > > > + <sect2> > > > > + <title>DPIO</title> > > > > +!Pdrivers/gpu/drm/i915/i915_reg.h DPIO > > > > + </sect2> > > > > </sect1> > > > > > > > > <sect1> > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > > > b/drivers/gpu/drm/i915/i915_reg.h index b6d5045..8e18e8f 100644 > > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > > @@ -566,12 +566,89 @@ enum punit_power_well { > > > > #define DSI_PLL_M1_DIV_MASK (0x1ff << 0) > > > > #define CCK_DISPLAY_CLOCK_CONTROL 0x6b > > > > > > > > -/* > > > > - * DPIO - a special bus for various display related registers to > > > > hide behind > > > > +/** > > This is something I miss out. The /** should be /* to match what you want to do in the first patch. No, this time around we really want this comment in the generated docs. > > Regards, > Chon Ming > > > > > + * DOC: DPIO > > > > + * > > > > + * VLV and CHV have slightly peculiar display PHYs for driving > > > > +DP/HDMI > > > > + * ports. DPIO is the name given to such a display PHY. These PHYs > > > > + * don't follow the standard programming model using direct MMIO > > > > + * registers, and instead their registers must be accessed trough > > > > +IOSF > > > > + * sideband. VLV has one such PHY for driving ports B and C, and > > > > +CHV > > > > + * adds another PHY for driving port D. Each PHY responds to > > > > +specific > > > > + * IOSF-SB port. > > > > + * > > > > + * Each display PHY is made up of one or two channels. Each channel > > > > + * houses a common lane part which contains the PLL and other > > > > +common > > > > + * logic. CH0 common lane also contains the IOSF-SB logic for the > > > > + * Common Register Interface (CRI) ie. the DPIO registers. CRI > > > > +clock > > > > + * must be running when any DPIO registers are accessed. > > > > + * > > > > + * In addition to having their own registers, the PHYs are also > > > > + * controlled through some dedicated signals from the display > > > > + * controller. These include PLL reference clock enable, PLL > > > > +enable, > > > > + * and CRI clock selection, for example. > > > > + * > > > > + * Eeach channel also has two splines (also called data lanes), and > > > > + * each spline is made up of one Physical Access Coding Sub-Layer > > > > + * (PCS) block and two TX lanes. So each channel has two PCS blocks > > > > + * and four TX lanes. The TX lanes are used as DP lanes or TMDS > > > > + * data/clock pairs depending on the output type. > > > > + * > > > > + * Additionally the PHY also contains an AUX lane with AUX blocks > > > > + * for each channel. This is used for DP AUX communication, but > > > > + * this fact isn't really relevant for the driver since AUX is > > > > + * controlled from the display controller side. No DPIO registers > > > > + * need to be accessed during AUX communication, > > > > + * > > > > + * Generally the common lane corresponds to the pipe and > > > > + * the spline (PCS/TX) correponds to the port. > > > > + * > > > > + * For dual channel PHY (VLV/CHV): > > > > + * > > > > + * pipe A == CMN/PLL/REF CH0 > > > > * > > > > - * DPIO is VLV only. > > > > + * pipe B == CMN/PLL/REF CH1 > > > > + * > > > > + * port B == PCS/TX CH0 > > > > + * > > > > + * port C == PCS/TX CH1 > > > > + * > > > > + * This is especially important when we cross the streams > > > > + * ie. drive port B with pipe B, or port C with pipe A. > > > > + * > > > > > > > > > Do you want to add something like the PHY actually allow PLL CH0 to > > > supply clock to both ports, same as PLL CH1. But this is something > > > i915 not supported yet, for power saving purpose. > > > > Maybe we can add the comment if and when we implement it. > > > > I'm not even sure if we should implement it since it might lead to blinking > > displays if we have to reroute the PLLs for active pipes. > > Although maybe it's possible to swap over to the pipe's own PLL from the > > shared case w/o blinking, but that would require special code in the modeset > > path since we'd need to make sure we fire up the new PLL first, then swap > > the PLLs, and only then can reprogram the old PLL. > > > > So unless the power savings are really significant I'm not sure anyone will > > bother with this. > > > > OTOH we already have potential display blinking due to the cdclk change logic, > > so maybe we don't care that much. > > > > > > > > > + * For single channel PHY (CHV): > > > > + * > > > > + * pipe C == CMN/PLL/REF CH0 > > > > + * > > > > + * port D == PCS/TX CH0 > > > > + * > > > > + * Note: digital port B is DDI0, digital port C is DDI1, > > > > + * digital port D is DDI2 > > > > + */ > > > > +/* > > > > + * Dual channel PHY (VLV/CHV) > > > > + * --------------------------------- > > > > + * | CH0 | CH1 | > > > > + * | CMN/PLL/REF | CMN/PLL/REF | > > > > > > There is a AUX for both CH0 and CH1. > > > > I left out AUX since the fact that it's part of the PHY isn't really significant for > > us. I did mention it in the text. > > > > > > > > Other than this, > > > > > > Reviewed-by: Chon Ming Lee <chon.ming.lee@intel.com> > > > > > > > > > > + * |---------------|---------------| Display PHY > > > > + * | PCS01 | PCS23 | PCS01 | PCS23 | > > > > + * |-------|-------|-------|-------| > > > > + * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| > > > > + * --------------------------------- > > > > + * | DDI0 | DDI1 | DP/HDMI ports > > > > + * --------------------------------- > > > > * > > > > - * Note: digital port B is DDI0, digital pot C is DDI1 > > > > + * Single channel PHY (CHV) > > > > + * ----------------- > > > > + * | CH0 | > > > > + * | CMN/PLL/REF | > > > > + * |---------------| Display PHY > > > > + * | PCS01 | PCS23 | > > > > + * |-------|-------| > > > > + * |TX0|TX1|TX2|TX3| > > > > + * ----------------- > > > > + * | DDI2 | DP/HDMI port > > > > + * ----------------- > > > > */ > > > > #define DPIO_DEVFN 0 > > > > #define DPIO_OPCODE_REG_WRITE 1 > > > > -- > > > > 1.8.3.2 > > > > > > > > _______________________________________________ > > > > Intel-gfx mailing list > > > > Intel-gfx@lists.freedesktop.org > > > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > > Ville Syrjälä > > Intel OTC -- Ville Syrjälä Intel OTC ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/3] drm/i915: Provide DPIO diagrams as docboox tables 2014-04-25 17:14 ` [PATCH 1/3] drm/i915: Drop /** */ comments from i915_reg.h ville.syrjala 2014-04-25 17:14 ` [PATCH v2 2/3] drm/i915: Add a brief description of the VLV display PHY internals ville.syrjala @ 2014-04-25 17:14 ` ville.syrjala 2014-05-21 10:54 ` Damien Lespiau 2014-05-21 10:59 ` Lee, Chon Ming 2014-05-20 14:13 ` [PATCH 1/3] drm/i915: Drop /** */ comments from i915_reg.h Damien Lespiau 2 siblings, 2 replies; 16+ messages in thread From: ville.syrjala @ 2014-04-25 17:14 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> The ascii art version of the DPIO diagram gets mangled by docbook, so we can't use it there. Insted provide another version built using <table>. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- Documentation/DocBook/drm.tmpl | 86 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl index e361ccd..bf11fe5 100644 --- a/Documentation/DocBook/drm.tmpl +++ b/Documentation/DocBook/drm.tmpl @@ -2945,6 +2945,92 @@ int num_ioctls;</synopsis> <sect2> <title>DPIO</title> !Pdrivers/gpu/drm/i915/i915_reg.h DPIO + <table id="dpiox2"> + <title>Dual channel PHY (VLV/CHV)</title> + <tgroup cols="8"> + <colspec colname="c0" /> + <colspec colname="c1" /> + <colspec colname="c2" /> + <colspec colname="c3" /> + <colspec colname="c4" /> + <colspec colname="c5" /> + <colspec colname="c6" /> + <colspec colname="c7" /> + <spanspec spanname="ch0" namest="c0" nameend="c3" /> + <spanspec spanname="ch1" namest="c4" nameend="c7" /> + <spanspec spanname="ch0pcs01" namest="c0" nameend="c1" /> + <spanspec spanname="ch0pcs23" namest="c2" nameend="c3" /> + <spanspec spanname="ch1pcs01" namest="c4" nameend="c5" /> + <spanspec spanname="ch1pcs23" namest="c6" nameend="c7" /> + <thead> + <row> + <entry spanname="ch0">CH0</entry> + <entry spanname="ch1">CH1</entry> + </row> + </thead> + <tbody valign="top" align="center"> + <row> + <entry spanname="ch0">CMN/PLL/REF</entry> + <entry spanname="ch1">CMN/PLL/REF</entry> + </row> + <row> + <entry spanname="ch0pcs01">PCS01</entry> + <entry spanname="ch0pcs23">PCS23</entry> + <entry spanname="ch1pcs01">PCS01</entry> + <entry spanname="ch1pcs23">PCS23</entry> + </row> + <row> + <entry>TX0</entry> + <entry>TX1</entry> + <entry>TX2</entry> + <entry>TX3</entry> + <entry>TX0</entry> + <entry>TX1</entry> + <entry>TX2</entry> + <entry>TX3</entry> + </row> + <row> + <entry spanname="ch0">DDI0</entry> + <entry spanname="ch1">DDI1</entry> + </row> + </tbody> + </tgroup> + </table> + <table id="dpiox1"> + <title>Single channel PHY (CHV)</title> + <tgroup cols="4"> + <colspec colname="c0" /> + <colspec colname="c1" /> + <colspec colname="c2" /> + <colspec colname="c3" /> + <spanspec spanname="ch0" namest="c0" nameend="c3" /> + <spanspec spanname="ch0pcs01" namest="c0" nameend="c1" /> + <spanspec spanname="ch0pcs23" namest="c2" nameend="c3" /> + <thead> + <row> + <entry spanname="ch0">CH0</entry> + </row> + </thead> + <tbody valign="top" align="center"> + <row> + <entry spanname="ch0">CMN/PLL/REF</entry> + </row> + <row> + <entry spanname="ch0pcs01">PCS01</entry> + <entry spanname="ch0pcs23">PCS23</entry> + </row> + <row> + <entry>TX0</entry> + <entry>TX1</entry> + <entry>TX2</entry> + <entry>TX3</entry> + </row> + <row> + <entry spanname="ch0">DDI2</entry> + </row> + </tbody> + </tgroup> + </table> </sect2> </sect1> -- 1.8.3.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 3/3] drm/i915: Provide DPIO diagrams as docboox tables 2014-04-25 17:14 ` [PATCH 3/3] drm/i915: Provide DPIO diagrams as docboox tables ville.syrjala @ 2014-05-21 10:54 ` Damien Lespiau 2014-05-21 10:59 ` Lee, Chon Ming 1 sibling, 0 replies; 16+ messages in thread From: Damien Lespiau @ 2014-05-21 10:54 UTC (permalink / raw) To: ville.syrjala; +Cc: intel-gfx On Fri, Apr 25, 2014 at 08:14:32PM +0300, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > The ascii art version of the DPIO diagram gets mangled by docbook, so > we can't use it there. Insted provide another version built using > <table>. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> I guess one could also add the AUX units here as well. But that's still way better than what we currently have. Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> -- Damien > --- > Documentation/DocBook/drm.tmpl | 86 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 86 insertions(+) > > diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl > index e361ccd..bf11fe5 100644 > --- a/Documentation/DocBook/drm.tmpl > +++ b/Documentation/DocBook/drm.tmpl > @@ -2945,6 +2945,92 @@ int num_ioctls;</synopsis> > <sect2> > <title>DPIO</title> > !Pdrivers/gpu/drm/i915/i915_reg.h DPIO > + <table id="dpiox2"> > + <title>Dual channel PHY (VLV/CHV)</title> > + <tgroup cols="8"> > + <colspec colname="c0" /> > + <colspec colname="c1" /> > + <colspec colname="c2" /> > + <colspec colname="c3" /> > + <colspec colname="c4" /> > + <colspec colname="c5" /> > + <colspec colname="c6" /> > + <colspec colname="c7" /> > + <spanspec spanname="ch0" namest="c0" nameend="c3" /> > + <spanspec spanname="ch1" namest="c4" nameend="c7" /> > + <spanspec spanname="ch0pcs01" namest="c0" nameend="c1" /> > + <spanspec spanname="ch0pcs23" namest="c2" nameend="c3" /> > + <spanspec spanname="ch1pcs01" namest="c4" nameend="c5" /> > + <spanspec spanname="ch1pcs23" namest="c6" nameend="c7" /> > + <thead> > + <row> > + <entry spanname="ch0">CH0</entry> > + <entry spanname="ch1">CH1</entry> > + </row> > + </thead> > + <tbody valign="top" align="center"> > + <row> > + <entry spanname="ch0">CMN/PLL/REF</entry> > + <entry spanname="ch1">CMN/PLL/REF</entry> > + </row> > + <row> > + <entry spanname="ch0pcs01">PCS01</entry> > + <entry spanname="ch0pcs23">PCS23</entry> > + <entry spanname="ch1pcs01">PCS01</entry> > + <entry spanname="ch1pcs23">PCS23</entry> > + </row> > + <row> > + <entry>TX0</entry> > + <entry>TX1</entry> > + <entry>TX2</entry> > + <entry>TX3</entry> > + <entry>TX0</entry> > + <entry>TX1</entry> > + <entry>TX2</entry> > + <entry>TX3</entry> > + </row> > + <row> > + <entry spanname="ch0">DDI0</entry> > + <entry spanname="ch1">DDI1</entry> > + </row> > + </tbody> > + </tgroup> > + </table> > + <table id="dpiox1"> > + <title>Single channel PHY (CHV)</title> > + <tgroup cols="4"> > + <colspec colname="c0" /> > + <colspec colname="c1" /> > + <colspec colname="c2" /> > + <colspec colname="c3" /> > + <spanspec spanname="ch0" namest="c0" nameend="c3" /> > + <spanspec spanname="ch0pcs01" namest="c0" nameend="c1" /> > + <spanspec spanname="ch0pcs23" namest="c2" nameend="c3" /> > + <thead> > + <row> > + <entry spanname="ch0">CH0</entry> > + </row> > + </thead> > + <tbody valign="top" align="center"> > + <row> > + <entry spanname="ch0">CMN/PLL/REF</entry> > + </row> > + <row> > + <entry spanname="ch0pcs01">PCS01</entry> > + <entry spanname="ch0pcs23">PCS23</entry> > + </row> > + <row> > + <entry>TX0</entry> > + <entry>TX1</entry> > + <entry>TX2</entry> > + <entry>TX3</entry> > + </row> > + <row> > + <entry spanname="ch0">DDI2</entry> > + </row> > + </tbody> > + </tgroup> > + </table> > </sect2> > </sect1> > > -- > 1.8.3.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/3] drm/i915: Provide DPIO diagrams as docboox tables 2014-04-25 17:14 ` [PATCH 3/3] drm/i915: Provide DPIO diagrams as docboox tables ville.syrjala 2014-05-21 10:54 ` Damien Lespiau @ 2014-05-21 10:59 ` Lee, Chon Ming 2014-05-21 12:18 ` Daniel Vetter 1 sibling, 1 reply; 16+ messages in thread From: Lee, Chon Ming @ 2014-05-21 10:59 UTC (permalink / raw) To: ville.syrjala; +Cc: intel-gfx On 04/25 20:14, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > The ascii art version of the DPIO diagram gets mangled by docbook, so > we can't use it there. Insted provide another version built using > <table>. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> When generating drm.tmpl to html, it say no structured comments found for i915_reg.h I am getting this error when displaying the link for i915_reg.h in HTML format: Document generation inconsistency. Not sure is some issue on my side because I have issue apply this patch series, so I apply manually. Anyway, the table below is similar to your previous patch. So, Reviewed-by: Chon Ming Lee <chon.ming.lee@intel.com> > --- > Documentation/DocBook/drm.tmpl | 86 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 86 insertions(+) > > diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl > index e361ccd..bf11fe5 100644 > --- a/Documentation/DocBook/drm.tmpl > +++ b/Documentation/DocBook/drm.tmpl > @@ -2945,6 +2945,92 @@ int num_ioctls;</synopsis> > <sect2> > <title>DPIO</title> > !Pdrivers/gpu/drm/i915/i915_reg.h DPIO > + <table id="dpiox2"> > + <title>Dual channel PHY (VLV/CHV)</title> > + <tgroup cols="8"> > + <colspec colname="c0" /> > + <colspec colname="c1" /> > + <colspec colname="c2" /> > + <colspec colname="c3" /> > + <colspec colname="c4" /> > + <colspec colname="c5" /> > + <colspec colname="c6" /> > + <colspec colname="c7" /> > + <spanspec spanname="ch0" namest="c0" nameend="c3" /> > + <spanspec spanname="ch1" namest="c4" nameend="c7" /> > + <spanspec spanname="ch0pcs01" namest="c0" nameend="c1" /> > + <spanspec spanname="ch0pcs23" namest="c2" nameend="c3" /> > + <spanspec spanname="ch1pcs01" namest="c4" nameend="c5" /> > + <spanspec spanname="ch1pcs23" namest="c6" nameend="c7" /> > + <thead> > + <row> > + <entry spanname="ch0">CH0</entry> > + <entry spanname="ch1">CH1</entry> > + </row> > + </thead> > + <tbody valign="top" align="center"> > + <row> > + <entry spanname="ch0">CMN/PLL/REF</entry> > + <entry spanname="ch1">CMN/PLL/REF</entry> > + </row> > + <row> > + <entry spanname="ch0pcs01">PCS01</entry> > + <entry spanname="ch0pcs23">PCS23</entry> > + <entry spanname="ch1pcs01">PCS01</entry> > + <entry spanname="ch1pcs23">PCS23</entry> > + </row> > + <row> > + <entry>TX0</entry> > + <entry>TX1</entry> > + <entry>TX2</entry> > + <entry>TX3</entry> > + <entry>TX0</entry> > + <entry>TX1</entry> > + <entry>TX2</entry> > + <entry>TX3</entry> > + </row> > + <row> > + <entry spanname="ch0">DDI0</entry> > + <entry spanname="ch1">DDI1</entry> > + </row> > + </tbody> > + </tgroup> > + </table> > + <table id="dpiox1"> > + <title>Single channel PHY (CHV)</title> > + <tgroup cols="4"> > + <colspec colname="c0" /> > + <colspec colname="c1" /> > + <colspec colname="c2" /> > + <colspec colname="c3" /> > + <spanspec spanname="ch0" namest="c0" nameend="c3" /> > + <spanspec spanname="ch0pcs01" namest="c0" nameend="c1" /> > + <spanspec spanname="ch0pcs23" namest="c2" nameend="c3" /> > + <thead> > + <row> > + <entry spanname="ch0">CH0</entry> > + </row> > + </thead> > + <tbody valign="top" align="center"> > + <row> > + <entry spanname="ch0">CMN/PLL/REF</entry> > + </row> > + <row> > + <entry spanname="ch0pcs01">PCS01</entry> > + <entry spanname="ch0pcs23">PCS23</entry> > + </row> > + <row> > + <entry>TX0</entry> > + <entry>TX1</entry> > + <entry>TX2</entry> > + <entry>TX3</entry> > + </row> > + <row> > + <entry spanname="ch0">DDI2</entry> > + </row> > + </tbody> > + </tgroup> > + </table> > </sect2> > </sect1> > > -- > 1.8.3.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/3] drm/i915: Provide DPIO diagrams as docboox tables 2014-05-21 10:59 ` Lee, Chon Ming @ 2014-05-21 12:18 ` Daniel Vetter 0 siblings, 0 replies; 16+ messages in thread From: Daniel Vetter @ 2014-05-21 12:18 UTC (permalink / raw) To: Lee, Chon Ming; +Cc: intel-gfx On Wed, May 21, 2014 at 06:59:03PM +0800, Lee, Chon Ming wrote: > On 04/25 20:14, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > The ascii art version of the DPIO diagram gets mangled by docbook, so > > we can't use it there. Insted provide another version built using > > <table>. > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > When generating drm.tmpl to html, it say no structured comments found for > i915_reg.h > > I am getting this error when displaying the link for i915_reg.h in HTML format: > Document generation inconsistency. > > Not sure is some issue on my side because I have issue apply this patch series, > so I apply manually. > > Anyway, the table below is similar to your previous patch. So, Worked here, dunno what's broken on your side ... Note that some docbooks moved around in 3.15-rc1 and the build system doesn't handle that. You need to run a git clean -dfx in the Documentation directory to fix that. > Reviewed-by: Chon Ming Lee <chon.ming.lee@intel.com> Both patches merged, thanks. -Daniel > > > --- > > Documentation/DocBook/drm.tmpl | 86 ++++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 86 insertions(+) > > > > diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl > > index e361ccd..bf11fe5 100644 > > --- a/Documentation/DocBook/drm.tmpl > > +++ b/Documentation/DocBook/drm.tmpl > > @@ -2945,6 +2945,92 @@ int num_ioctls;</synopsis> > > <sect2> > > <title>DPIO</title> > > !Pdrivers/gpu/drm/i915/i915_reg.h DPIO > > + <table id="dpiox2"> > > + <title>Dual channel PHY (VLV/CHV)</title> > > + <tgroup cols="8"> > > + <colspec colname="c0" /> > > + <colspec colname="c1" /> > > + <colspec colname="c2" /> > > + <colspec colname="c3" /> > > + <colspec colname="c4" /> > > + <colspec colname="c5" /> > > + <colspec colname="c6" /> > > + <colspec colname="c7" /> > > + <spanspec spanname="ch0" namest="c0" nameend="c3" /> > > + <spanspec spanname="ch1" namest="c4" nameend="c7" /> > > + <spanspec spanname="ch0pcs01" namest="c0" nameend="c1" /> > > + <spanspec spanname="ch0pcs23" namest="c2" nameend="c3" /> > > + <spanspec spanname="ch1pcs01" namest="c4" nameend="c5" /> > > + <spanspec spanname="ch1pcs23" namest="c6" nameend="c7" /> > > + <thead> > > + <row> > > + <entry spanname="ch0">CH0</entry> > > + <entry spanname="ch1">CH1</entry> > > + </row> > > + </thead> > > + <tbody valign="top" align="center"> > > + <row> > > + <entry spanname="ch0">CMN/PLL/REF</entry> > > + <entry spanname="ch1">CMN/PLL/REF</entry> > > + </row> > > + <row> > > + <entry spanname="ch0pcs01">PCS01</entry> > > + <entry spanname="ch0pcs23">PCS23</entry> > > + <entry spanname="ch1pcs01">PCS01</entry> > > + <entry spanname="ch1pcs23">PCS23</entry> > > + </row> > > + <row> > > + <entry>TX0</entry> > > + <entry>TX1</entry> > > + <entry>TX2</entry> > > + <entry>TX3</entry> > > + <entry>TX0</entry> > > + <entry>TX1</entry> > > + <entry>TX2</entry> > > + <entry>TX3</entry> > > + </row> > > + <row> > > + <entry spanname="ch0">DDI0</entry> > > + <entry spanname="ch1">DDI1</entry> > > + </row> > > + </tbody> > > + </tgroup> > > + </table> > > + <table id="dpiox1"> > > + <title>Single channel PHY (CHV)</title> > > + <tgroup cols="4"> > > + <colspec colname="c0" /> > > + <colspec colname="c1" /> > > + <colspec colname="c2" /> > > + <colspec colname="c3" /> > > + <spanspec spanname="ch0" namest="c0" nameend="c3" /> > > + <spanspec spanname="ch0pcs01" namest="c0" nameend="c1" /> > > + <spanspec spanname="ch0pcs23" namest="c2" nameend="c3" /> > > + <thead> > > + <row> > > + <entry spanname="ch0">CH0</entry> > > + </row> > > + </thead> > > + <tbody valign="top" align="center"> > > + <row> > > + <entry spanname="ch0">CMN/PLL/REF</entry> > > + </row> > > + <row> > > + <entry spanname="ch0pcs01">PCS01</entry> > > + <entry spanname="ch0pcs23">PCS23</entry> > > + </row> > > + <row> > > + <entry>TX0</entry> > > + <entry>TX1</entry> > > + <entry>TX2</entry> > > + <entry>TX3</entry> > > + </row> > > + <row> > > + <entry spanname="ch0">DDI2</entry> > > + </row> > > + </tbody> > > + </tgroup> > > + </table> > > </sect2> > > </sect1> > > > > -- > > 1.8.3.2 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/3] drm/i915: Drop /** */ comments from i915_reg.h 2014-04-25 17:14 ` [PATCH 1/3] drm/i915: Drop /** */ comments from i915_reg.h ville.syrjala 2014-04-25 17:14 ` [PATCH v2 2/3] drm/i915: Add a brief description of the VLV display PHY internals ville.syrjala 2014-04-25 17:14 ` [PATCH 3/3] drm/i915: Provide DPIO diagrams as docboox tables ville.syrjala @ 2014-05-20 14:13 ` Damien Lespiau 2 siblings, 0 replies; 16+ messages in thread From: Damien Lespiau @ 2014-05-20 14:13 UTC (permalink / raw) To: ville.syrjala; +Cc: intel-gfx On Fri, Apr 25, 2014 at 08:14:30PM +0300, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > The comments in i915_reg.h aren't proper kernel-doc comments, so replace > the magic /** with just /* > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> -- Damien > --- > drivers/gpu/drm/i915/i915_reg.h | 246 ++++++++++++++++++++-------------------- > 1 file changed, 123 insertions(+), 123 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 0eff337..b6d5045 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1516,7 +1516,7 @@ enum punit_power_well { > # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ > # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) > # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) > -/** > +/* > * This bit must be set on the 830 to prevent hangs when turning off the > * overlay scaler. > */ > @@ -1536,12 +1536,12 @@ enum punit_power_well { > # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) > # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) > # define MAG_CLOCK_GATE_DISABLE (1 << 5) > -/** This bit must be unset on 855,865 */ > +/* This bit must be unset on 855,865 */ > # define MECI_CLOCK_GATE_DISABLE (1 << 4) > # define DCMP_CLOCK_GATE_DISABLE (1 << 3) > # define MEC_CLOCK_GATE_DISABLE (1 << 2) > # define MECO_CLOCK_GATE_DISABLE (1 << 1) > -/** This bit must be set on 855,865. */ > +/* This bit must be set on 855,865. */ > # define SV_CLOCK_GATE_DISABLE (1 << 0) > # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) > # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) > @@ -1562,14 +1562,14 @@ enum punit_power_well { > # define I915_BY_CLOCK_GATE_DISABLE (1 << 0) > > # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) > -/** This bit must always be set on 965G/965GM */ > +/* This bit must always be set on 965G/965GM */ > # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) > # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) > # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) > # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) > # define I965_GW_CLOCK_GATE_DISABLE (1 << 25) > # define I965_TD_CLOCK_GATE_DISABLE (1 << 24) > -/** This bit must always be set on 965G */ > +/* This bit must always be set on 965G */ > # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) > # define I965_IC_CLOCK_GATE_DISABLE (1 << 22) > # define I965_EU_CLOCK_GATE_DISABLE (1 << 21) > @@ -1635,7 +1635,7 @@ enum punit_power_well { > /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ > #define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04) > > -/** 915-945 and GM965 MCH register controlling DRAM channel access */ > +/* 915-945 and GM965 MCH register controlling DRAM channel access */ > #define DCC 0x10200 > #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) > #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) > @@ -1644,15 +1644,15 @@ enum punit_power_well { > #define DCC_CHANNEL_XOR_DISABLE (1 << 10) > #define DCC_CHANNEL_XOR_BIT_17 (1 << 9) > > -/** Pineview MCH register contains DDR3 setting */ > +/* Pineview MCH register contains DDR3 setting */ > #define CSHRDDR3CTL 0x101a8 > #define CSHRDDR3CTL_DDR3 (1 << 2) > > -/** 965 MCH register controlling DRAM channel configuration */ > +/* 965 MCH register controlling DRAM channel configuration */ > #define C0DRB3 0x10206 > #define C1DRB3 0x10606 > > -/** snb MCH registers for reading the DRAM channel configuration */ > +/* snb MCH registers for reading the DRAM channel configuration */ > #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004) > #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008) > #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C) > @@ -1674,7 +1674,7 @@ enum punit_power_well { > #define MAD_DIMM_A_SIZE_SHIFT 0 > #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) > > -/** snb MCH registers for priority tuning */ > +/* snb MCH registers for priority tuning */ > #define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10) > #define MCH_SSKPD_WM0_MASK 0x3f > #define MCH_SSKPD_WM0_VAL 0xc > @@ -2346,7 +2346,7 @@ enum punit_power_well { > #define SDVO_PIPE_B_SELECT (1 << 30) > #define SDVO_STALL_SELECT (1 << 29) > #define SDVO_INTERRUPT_ENABLE (1 << 26) > -/** > +/* > * 915G/GM SDVO pixel multiplier. > * Programmed value is multiplier - 1, up to 5x. > * \sa DPLL_MD_UDI_MULTIPLIER_MASK > @@ -2656,65 +2656,65 @@ enum punit_power_well { > > /* TV port control */ > #define TV_CTL 0x68000 > -/** Enables the TV encoder */ > +/* Enables the TV encoder */ > # define TV_ENC_ENABLE (1 << 31) > -/** Sources the TV encoder input from pipe B instead of A. */ > +/* Sources the TV encoder input from pipe B instead of A. */ > # define TV_ENC_PIPEB_SELECT (1 << 30) > -/** Outputs composite video (DAC A only) */ > +/* Outputs composite video (DAC A only) */ > # define TV_ENC_OUTPUT_COMPOSITE (0 << 28) > -/** Outputs SVideo video (DAC B/C) */ > +/* Outputs SVideo video (DAC B/C) */ > # define TV_ENC_OUTPUT_SVIDEO (1 << 28) > -/** Outputs Component video (DAC A/B/C) */ > +/* Outputs Component video (DAC A/B/C) */ > # define TV_ENC_OUTPUT_COMPONENT (2 << 28) > -/** Outputs Composite and SVideo (DAC A/B/C) */ > +/* Outputs Composite and SVideo (DAC A/B/C) */ > # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) > # define TV_TRILEVEL_SYNC (1 << 21) > -/** Enables slow sync generation (945GM only) */ > +/* Enables slow sync generation (945GM only) */ > # define TV_SLOW_SYNC (1 << 20) > -/** Selects 4x oversampling for 480i and 576p */ > +/* Selects 4x oversampling for 480i and 576p */ > # define TV_OVERSAMPLE_4X (0 << 18) > -/** Selects 2x oversampling for 720p and 1080i */ > +/* Selects 2x oversampling for 720p and 1080i */ > # define TV_OVERSAMPLE_2X (1 << 18) > -/** Selects no oversampling for 1080p */ > +/* Selects no oversampling for 1080p */ > # define TV_OVERSAMPLE_NONE (2 << 18) > -/** Selects 8x oversampling */ > +/* Selects 8x oversampling */ > # define TV_OVERSAMPLE_8X (3 << 18) > -/** Selects progressive mode rather than interlaced */ > +/* Selects progressive mode rather than interlaced */ > # define TV_PROGRESSIVE (1 << 17) > -/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */ > +/* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ > # define TV_PAL_BURST (1 << 16) > -/** Field for setting delay of Y compared to C */ > +/* Field for setting delay of Y compared to C */ > # define TV_YC_SKEW_MASK (7 << 12) > -/** Enables a fix for 480p/576p standard definition modes on the 915GM only */ > +/* Enables a fix for 480p/576p standard definition modes on the 915GM only */ > # define TV_ENC_SDP_FIX (1 << 11) > -/** > +/* > * Enables a fix for the 915GM only. > * > * Not sure what it does. > */ > # define TV_ENC_C0_FIX (1 << 10) > -/** Bits that must be preserved by software */ > +/* Bits that must be preserved by software */ > # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) > # define TV_FUSE_STATE_MASK (3 << 4) > -/** Read-only state that reports all features enabled */ > +/* Read-only state that reports all features enabled */ > # define TV_FUSE_STATE_ENABLED (0 << 4) > -/** Read-only state that reports that Macrovision is disabled in hardware*/ > +/* Read-only state that reports that Macrovision is disabled in hardware*/ > # define TV_FUSE_STATE_NO_MACROVISION (1 << 4) > -/** Read-only state that reports that TV-out is disabled in hardware. */ > +/* Read-only state that reports that TV-out is disabled in hardware. */ > # define TV_FUSE_STATE_DISABLED (2 << 4) > -/** Normal operation */ > +/* Normal operation */ > # define TV_TEST_MODE_NORMAL (0 << 0) > -/** Encoder test pattern 1 - combo pattern */ > +/* Encoder test pattern 1 - combo pattern */ > # define TV_TEST_MODE_PATTERN_1 (1 << 0) > -/** Encoder test pattern 2 - full screen vertical 75% color bars */ > +/* Encoder test pattern 2 - full screen vertical 75% color bars */ > # define TV_TEST_MODE_PATTERN_2 (2 << 0) > -/** Encoder test pattern 3 - full screen horizontal 75% color bars */ > +/* Encoder test pattern 3 - full screen horizontal 75% color bars */ > # define TV_TEST_MODE_PATTERN_3 (3 << 0) > -/** Encoder test pattern 4 - random noise */ > +/* Encoder test pattern 4 - random noise */ > # define TV_TEST_MODE_PATTERN_4 (4 << 0) > -/** Encoder test pattern 5 - linear color ramps */ > +/* Encoder test pattern 5 - linear color ramps */ > # define TV_TEST_MODE_PATTERN_5 (5 << 0) > -/** > +/* > * This test mode forces the DACs to 50% of full output. > * > * This is used for load detection in combination with TVDAC_SENSE_MASK > @@ -2724,35 +2724,35 @@ enum punit_power_well { > > #define TV_DAC 0x68004 > # define TV_DAC_SAVE 0x00ffff00 > -/** > +/* > * Reports that DAC state change logic has reported change (RO). > * > * This gets cleared when TV_DAC_STATE_EN is cleared > */ > # define TVDAC_STATE_CHG (1 << 31) > # define TVDAC_SENSE_MASK (7 << 28) > -/** Reports that DAC A voltage is above the detect threshold */ > +/* Reports that DAC A voltage is above the detect threshold */ > # define TVDAC_A_SENSE (1 << 30) > -/** Reports that DAC B voltage is above the detect threshold */ > +/* Reports that DAC B voltage is above the detect threshold */ > # define TVDAC_B_SENSE (1 << 29) > -/** Reports that DAC C voltage is above the detect threshold */ > +/* Reports that DAC C voltage is above the detect threshold */ > # define TVDAC_C_SENSE (1 << 28) > -/** > +/* > * Enables DAC state detection logic, for load-based TV detection. > * > * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set > * to off, for load detection to work. > */ > # define TVDAC_STATE_CHG_EN (1 << 27) > -/** Sets the DAC A sense value to high */ > +/* Sets the DAC A sense value to high */ > # define TVDAC_A_SENSE_CTL (1 << 26) > -/** Sets the DAC B sense value to high */ > +/* Sets the DAC B sense value to high */ > # define TVDAC_B_SENSE_CTL (1 << 25) > -/** Sets the DAC C sense value to high */ > +/* Sets the DAC C sense value to high */ > # define TVDAC_C_SENSE_CTL (1 << 24) > -/** Overrides the ENC_ENABLE and DAC voltage levels */ > +/* Overrides the ENC_ENABLE and DAC voltage levels */ > # define DAC_CTL_OVERRIDE (1 << 7) > -/** Sets the slew rate. Must be preserved in software */ > +/* Sets the slew rate. Must be preserved in software */ > # define ENC_TVDAC_SLEW_FAST (1 << 6) > # define DAC_A_1_3_V (0 << 4) > # define DAC_A_1_1_V (1 << 4) > @@ -2767,7 +2767,7 @@ enum punit_power_well { > # define DAC_C_0_7_V (2 << 0) > # define DAC_C_MASK (3 << 0) > > -/** > +/* > * CSC coefficients are stored in a floating point format with 9 bits of > * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, > * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with > @@ -2782,7 +2782,7 @@ enum punit_power_well { > #define TV_CSC_Y2 0x68014 > # define TV_BY_MASK 0x07ff0000 > # define TV_BY_SHIFT 16 > -/** > +/* > * Y attenuation for component video. > * > * Stored in 1.9 fixed point. > @@ -2799,7 +2799,7 @@ enum punit_power_well { > #define TV_CSC_U2 0x6801c > # define TV_BU_MASK 0x07ff0000 > # define TV_BU_SHIFT 16 > -/** > +/* > * U attenuation for component video. > * > * Stored in 1.9 fixed point. > @@ -2816,7 +2816,7 @@ enum punit_power_well { > #define TV_CSC_V2 0x68024 > # define TV_BV_MASK 0x07ff0000 > # define TV_BV_SHIFT 16 > -/** > +/* > * V attenuation for component video. > * > * Stored in 1.9 fixed point. > @@ -2825,74 +2825,74 @@ enum punit_power_well { > # define TV_AV_SHIFT 0 > > #define TV_CLR_KNOBS 0x68028 > -/** 2s-complement brightness adjustment */ > +/* 2s-complement brightness adjustment */ > # define TV_BRIGHTNESS_MASK 0xff000000 > # define TV_BRIGHTNESS_SHIFT 24 > -/** Contrast adjustment, as a 2.6 unsigned floating point number */ > +/* Contrast adjustment, as a 2.6 unsigned floating point number */ > # define TV_CONTRAST_MASK 0x00ff0000 > # define TV_CONTRAST_SHIFT 16 > -/** Saturation adjustment, as a 2.6 unsigned floating point number */ > +/* Saturation adjustment, as a 2.6 unsigned floating point number */ > # define TV_SATURATION_MASK 0x0000ff00 > # define TV_SATURATION_SHIFT 8 > -/** Hue adjustment, as an integer phase angle in degrees */ > +/* Hue adjustment, as an integer phase angle in degrees */ > # define TV_HUE_MASK 0x000000ff > # define TV_HUE_SHIFT 0 > > #define TV_CLR_LEVEL 0x6802c > -/** Controls the DAC level for black */ > +/* Controls the DAC level for black */ > # define TV_BLACK_LEVEL_MASK 0x01ff0000 > # define TV_BLACK_LEVEL_SHIFT 16 > -/** Controls the DAC level for blanking */ > +/* Controls the DAC level for blanking */ > # define TV_BLANK_LEVEL_MASK 0x000001ff > # define TV_BLANK_LEVEL_SHIFT 0 > > #define TV_H_CTL_1 0x68030 > -/** Number of pixels in the hsync. */ > +/* Number of pixels in the hsync. */ > # define TV_HSYNC_END_MASK 0x1fff0000 > # define TV_HSYNC_END_SHIFT 16 > -/** Total number of pixels minus one in the line (display and blanking). */ > +/* Total number of pixels minus one in the line (display and blanking). */ > # define TV_HTOTAL_MASK 0x00001fff > # define TV_HTOTAL_SHIFT 0 > > #define TV_H_CTL_2 0x68034 > -/** Enables the colorburst (needed for non-component color) */ > +/* Enables the colorburst (needed for non-component color) */ > # define TV_BURST_ENA (1 << 31) > -/** Offset of the colorburst from the start of hsync, in pixels minus one. */ > +/* Offset of the colorburst from the start of hsync, in pixels minus one. */ > # define TV_HBURST_START_SHIFT 16 > # define TV_HBURST_START_MASK 0x1fff0000 > -/** Length of the colorburst */ > +/* Length of the colorburst */ > # define TV_HBURST_LEN_SHIFT 0 > # define TV_HBURST_LEN_MASK 0x0001fff > > #define TV_H_CTL_3 0x68038 > -/** End of hblank, measured in pixels minus one from start of hsync */ > +/* End of hblank, measured in pixels minus one from start of hsync */ > # define TV_HBLANK_END_SHIFT 16 > # define TV_HBLANK_END_MASK 0x1fff0000 > -/** Start of hblank, measured in pixels minus one from start of hsync */ > +/* Start of hblank, measured in pixels minus one from start of hsync */ > # define TV_HBLANK_START_SHIFT 0 > # define TV_HBLANK_START_MASK 0x0001fff > > #define TV_V_CTL_1 0x6803c > -/** XXX */ > +/* XXX */ > # define TV_NBR_END_SHIFT 16 > # define TV_NBR_END_MASK 0x07ff0000 > -/** XXX */ > +/* XXX */ > # define TV_VI_END_F1_SHIFT 8 > # define TV_VI_END_F1_MASK 0x00003f00 > -/** XXX */ > +/* XXX */ > # define TV_VI_END_F2_SHIFT 0 > # define TV_VI_END_F2_MASK 0x0000003f > > #define TV_V_CTL_2 0x68040 > -/** Length of vsync, in half lines */ > +/* Length of vsync, in half lines */ > # define TV_VSYNC_LEN_MASK 0x07ff0000 > # define TV_VSYNC_LEN_SHIFT 16 > -/** Offset of the start of vsync in field 1, measured in one less than the > +/* Offset of the start of vsync in field 1, measured in one less than the > * number of half lines. > */ > # define TV_VSYNC_START_F1_MASK 0x00007f00 > # define TV_VSYNC_START_F1_SHIFT 8 > -/** > +/* > * Offset of the start of vsync in field 2, measured in one less than the > * number of half lines. > */ > @@ -2900,17 +2900,17 @@ enum punit_power_well { > # define TV_VSYNC_START_F2_SHIFT 0 > > #define TV_V_CTL_3 0x68044 > -/** Enables generation of the equalization signal */ > +/* Enables generation of the equalization signal */ > # define TV_EQUAL_ENA (1 << 31) > -/** Length of vsync, in half lines */ > +/* Length of vsync, in half lines */ > # define TV_VEQ_LEN_MASK 0x007f0000 > # define TV_VEQ_LEN_SHIFT 16 > -/** Offset of the start of equalization in field 1, measured in one less than > +/* Offset of the start of equalization in field 1, measured in one less than > * the number of half lines. > */ > # define TV_VEQ_START_F1_MASK 0x0007f00 > # define TV_VEQ_START_F1_SHIFT 8 > -/** > +/* > * Offset of the start of equalization in field 2, measured in one less than > * the number of half lines. > */ > @@ -2918,13 +2918,13 @@ enum punit_power_well { > # define TV_VEQ_START_F2_SHIFT 0 > > #define TV_V_CTL_4 0x68048 > -/** > +/* > * Offset to start of vertical colorburst, measured in one less than the > * number of lines from vertical start. > */ > # define TV_VBURST_START_F1_MASK 0x003f0000 > # define TV_VBURST_START_F1_SHIFT 16 > -/** > +/* > * Offset to the end of vertical colorburst, measured in one less than the > * number of lines from the start of NBR. > */ > @@ -2932,13 +2932,13 @@ enum punit_power_well { > # define TV_VBURST_END_F1_SHIFT 0 > > #define TV_V_CTL_5 0x6804c > -/** > +/* > * Offset to start of vertical colorburst, measured in one less than the > * number of lines from vertical start. > */ > # define TV_VBURST_START_F2_MASK 0x003f0000 > # define TV_VBURST_START_F2_SHIFT 16 > -/** > +/* > * Offset to the end of vertical colorburst, measured in one less than the > * number of lines from the start of NBR. > */ > @@ -2946,13 +2946,13 @@ enum punit_power_well { > # define TV_VBURST_END_F2_SHIFT 0 > > #define TV_V_CTL_6 0x68050 > -/** > +/* > * Offset to start of vertical colorburst, measured in one less than the > * number of lines from vertical start. > */ > # define TV_VBURST_START_F3_MASK 0x003f0000 > # define TV_VBURST_START_F3_SHIFT 16 > -/** > +/* > * Offset to the end of vertical colorburst, measured in one less than the > * number of lines from the start of NBR. > */ > @@ -2960,13 +2960,13 @@ enum punit_power_well { > # define TV_VBURST_END_F3_SHIFT 0 > > #define TV_V_CTL_7 0x68054 > -/** > +/* > * Offset to start of vertical colorburst, measured in one less than the > * number of lines from vertical start. > */ > # define TV_VBURST_START_F4_MASK 0x003f0000 > # define TV_VBURST_START_F4_SHIFT 16 > -/** > +/* > * Offset to the end of vertical colorburst, measured in one less than the > * number of lines from the start of NBR. > */ > @@ -2974,56 +2974,56 @@ enum punit_power_well { > # define TV_VBURST_END_F4_SHIFT 0 > > #define TV_SC_CTL_1 0x68060 > -/** Turns on the first subcarrier phase generation DDA */ > +/* Turns on the first subcarrier phase generation DDA */ > # define TV_SC_DDA1_EN (1 << 31) > -/** Turns on the first subcarrier phase generation DDA */ > +/* Turns on the first subcarrier phase generation DDA */ > # define TV_SC_DDA2_EN (1 << 30) > -/** Turns on the first subcarrier phase generation DDA */ > +/* Turns on the first subcarrier phase generation DDA */ > # define TV_SC_DDA3_EN (1 << 29) > -/** Sets the subcarrier DDA to reset frequency every other field */ > +/* Sets the subcarrier DDA to reset frequency every other field */ > # define TV_SC_RESET_EVERY_2 (0 << 24) > -/** Sets the subcarrier DDA to reset frequency every fourth field */ > +/* Sets the subcarrier DDA to reset frequency every fourth field */ > # define TV_SC_RESET_EVERY_4 (1 << 24) > -/** Sets the subcarrier DDA to reset frequency every eighth field */ > +/* Sets the subcarrier DDA to reset frequency every eighth field */ > # define TV_SC_RESET_EVERY_8 (2 << 24) > -/** Sets the subcarrier DDA to never reset the frequency */ > +/* Sets the subcarrier DDA to never reset the frequency */ > # define TV_SC_RESET_NEVER (3 << 24) > -/** Sets the peak amplitude of the colorburst.*/ > +/* Sets the peak amplitude of the colorburst.*/ > # define TV_BURST_LEVEL_MASK 0x00ff0000 > # define TV_BURST_LEVEL_SHIFT 16 > -/** Sets the increment of the first subcarrier phase generation DDA */ > +/* Sets the increment of the first subcarrier phase generation DDA */ > # define TV_SCDDA1_INC_MASK 0x00000fff > # define TV_SCDDA1_INC_SHIFT 0 > > #define TV_SC_CTL_2 0x68064 > -/** Sets the rollover for the second subcarrier phase generation DDA */ > +/* Sets the rollover for the second subcarrier phase generation DDA */ > # define TV_SCDDA2_SIZE_MASK 0x7fff0000 > # define TV_SCDDA2_SIZE_SHIFT 16 > -/** Sets the increent of the second subcarrier phase generation DDA */ > +/* Sets the increent of the second subcarrier phase generation DDA */ > # define TV_SCDDA2_INC_MASK 0x00007fff > # define TV_SCDDA2_INC_SHIFT 0 > > #define TV_SC_CTL_3 0x68068 > -/** Sets the rollover for the third subcarrier phase generation DDA */ > +/* Sets the rollover for the third subcarrier phase generation DDA */ > # define TV_SCDDA3_SIZE_MASK 0x7fff0000 > # define TV_SCDDA3_SIZE_SHIFT 16 > -/** Sets the increent of the third subcarrier phase generation DDA */ > +/* Sets the increent of the third subcarrier phase generation DDA */ > # define TV_SCDDA3_INC_MASK 0x00007fff > # define TV_SCDDA3_INC_SHIFT 0 > > #define TV_WIN_POS 0x68070 > -/** X coordinate of the display from the start of horizontal active */ > +/* X coordinate of the display from the start of horizontal active */ > # define TV_XPOS_MASK 0x1fff0000 > # define TV_XPOS_SHIFT 16 > -/** Y coordinate of the display from the start of vertical active (NBR) */ > +/* Y coordinate of the display from the start of vertical active (NBR) */ > # define TV_YPOS_MASK 0x00000fff > # define TV_YPOS_SHIFT 0 > > #define TV_WIN_SIZE 0x68074 > -/** Horizontal size of the display window, measured in pixels*/ > +/* Horizontal size of the display window, measured in pixels*/ > # define TV_XSIZE_MASK 0x1fff0000 > # define TV_XSIZE_SHIFT 16 > -/** > +/* > * Vertical size of the display window, measured in pixels. > * > * Must be even for interlaced modes. > @@ -3032,28 +3032,28 @@ enum punit_power_well { > # define TV_YSIZE_SHIFT 0 > > #define TV_FILTER_CTL_1 0x68080 > -/** > +/* > * Enables automatic scaling calculation. > * > * If set, the rest of the registers are ignored, and the calculated values can > * be read back from the register. > */ > # define TV_AUTO_SCALE (1 << 31) > -/** > +/* > * Disables the vertical filter. > * > * This is required on modes more than 1024 pixels wide */ > # define TV_V_FILTER_BYPASS (1 << 29) > -/** Enables adaptive vertical filtering */ > +/* Enables adaptive vertical filtering */ > # define TV_VADAPT (1 << 28) > # define TV_VADAPT_MODE_MASK (3 << 26) > -/** Selects the least adaptive vertical filtering mode */ > +/* Selects the least adaptive vertical filtering mode */ > # define TV_VADAPT_MODE_LEAST (0 << 26) > -/** Selects the moderately adaptive vertical filtering mode */ > +/* Selects the moderately adaptive vertical filtering mode */ > # define TV_VADAPT_MODE_MODERATE (1 << 26) > -/** Selects the most adaptive vertical filtering mode */ > +/* Selects the most adaptive vertical filtering mode */ > # define TV_VADAPT_MODE_MOST (3 << 26) > -/** > +/* > * Sets the horizontal scaling factor. > * > * This should be the fractional part of the horizontal scaling factor divided > @@ -3065,14 +3065,14 @@ enum punit_power_well { > # define TV_HSCALE_FRAC_SHIFT 0 > > #define TV_FILTER_CTL_2 0x68084 > -/** > +/* > * Sets the integer part of the 3.15 fixed-point vertical scaling factor. > * > * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) > */ > # define TV_VSCALE_INT_MASK 0x00038000 > # define TV_VSCALE_INT_SHIFT 15 > -/** > +/* > * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. > * > * \sa TV_VSCALE_INT_MASK > @@ -3081,7 +3081,7 @@ enum punit_power_well { > # define TV_VSCALE_FRAC_SHIFT 0 > > #define TV_FILTER_CTL_3 0x68088 > -/** > +/* > * Sets the integer part of the 3.15 fixed-point vertical scaling factor. > * > * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) > @@ -3090,7 +3090,7 @@ enum punit_power_well { > */ > # define TV_VSCALE_IP_INT_MASK 0x00038000 > # define TV_VSCALE_IP_INT_SHIFT 15 > -/** > +/* > * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. > * > * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. > @@ -3102,26 +3102,26 @@ enum punit_power_well { > > #define TV_CC_CONTROL 0x68090 > # define TV_CC_ENABLE (1 << 31) > -/** > +/* > * Specifies which field to send the CC data in. > * > * CC data is usually sent in field 0. > */ > # define TV_CC_FID_MASK (1 << 27) > # define TV_CC_FID_SHIFT 27 > -/** Sets the horizontal position of the CC data. Usually 135. */ > +/* Sets the horizontal position of the CC data. Usually 135. */ > # define TV_CC_HOFF_MASK 0x03ff0000 > # define TV_CC_HOFF_SHIFT 16 > -/** Sets the vertical position of the CC data. Usually 21 */ > +/* Sets the vertical position of the CC data. Usually 21 */ > # define TV_CC_LINE_MASK 0x0000003f > # define TV_CC_LINE_SHIFT 0 > > #define TV_CC_DATA 0x68094 > # define TV_CC_RDY (1 << 31) > -/** Second word of CC data to be transmitted. */ > +/* Second word of CC data to be transmitted. */ > # define TV_CC_DATA_2_MASK 0x007f0000 > # define TV_CC_DATA_2_SHIFT 16 > -/** First word of CC data to be transmitted. */ > +/* First word of CC data to be transmitted. */ > # define TV_CC_DATA_1_MASK 0x0000007f > # define TV_CC_DATA_1_SHIFT 0 > > @@ -3190,32 +3190,32 @@ enum punit_power_well { > #define DP_PLL_FREQ_160MHZ (1 << 16) > #define DP_PLL_FREQ_MASK (3 << 16) > > -/** locked once port is enabled */ > +/* locked once port is enabled */ > #define DP_PORT_REVERSAL (1 << 15) > > /* eDP */ > #define DP_PLL_ENABLE (1 << 14) > > -/** sends the clock on lane 15 of the PEG for debug */ > +/* sends the clock on lane 15 of the PEG for debug */ > #define DP_CLOCK_OUTPUT_ENABLE (1 << 13) > > #define DP_SCRAMBLING_DISABLE (1 << 12) > #define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) > > -/** limit RGB values to avoid confusing TVs */ > +/* limit RGB values to avoid confusing TVs */ > #define DP_COLOR_RANGE_16_235 (1 << 8) > > -/** Turn on the audio link */ > +/* Turn on the audio link */ > #define DP_AUDIO_OUTPUT_ENABLE (1 << 6) > > -/** vs and hs sync polarity */ > +/* vs and hs sync polarity */ > #define DP_SYNC_VS_HIGH (1 << 4) > #define DP_SYNC_HS_HIGH (1 << 3) > > -/** A fantasy */ > +/* A fantasy */ > #define DP_DETECTED (1 << 2) > > -/** The aux channel provides a way to talk to the > +/* The aux channel provides a way to talk to the > * signal sink for DDC etc. Max packet size supported > * is 20 bytes in each direction, hence the 5 fixed > * data registers > -- > 1.8.3.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2014-05-21 12:18 UTC | newest] Thread overview: 16+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-04-25 13:32 [PATCH] drm/i915: Add a brief description of the VLV display PHY internals ville.syrjala 2014-04-25 14:01 ` Daniel Vetter 2014-04-25 14:01 ` Daniel Vetter 2014-04-25 17:14 ` [PATCH 1/3] drm/i915: Drop /** */ comments from i915_reg.h ville.syrjala 2014-04-25 17:14 ` [PATCH v2 2/3] drm/i915: Add a brief description of the VLV display PHY internals ville.syrjala 2014-04-25 17:44 ` Daniel Vetter 2014-05-20 14:18 ` Daniel Vetter 2014-05-21 8:31 ` Lee, Chon Ming 2014-05-21 8:49 ` Ville Syrjälä 2014-05-21 9:58 ` Lee, Chon Ming 2014-05-21 10:31 ` Ville Syrjälä 2014-04-25 17:14 ` [PATCH 3/3] drm/i915: Provide DPIO diagrams as docboox tables ville.syrjala 2014-05-21 10:54 ` Damien Lespiau 2014-05-21 10:59 ` Lee, Chon Ming 2014-05-21 12:18 ` Daniel Vetter 2014-05-20 14:13 ` [PATCH 1/3] drm/i915: Drop /** */ comments from i915_reg.h Damien Lespiau
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