From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 6/6] drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elk Date: Thu, 22 May 2014 16:35:33 +0200 Message-ID: <20140522143533.GU14357@phenom.ffwll.local> References: <1400516607-25840-1-git-send-email-ville.syrjala@linux.intel.com> <1400516607-25840-7-git-send-email-ville.syrjala@linux.intel.com> <20140520114645.4e04370f@jbarnes-desktop> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ee0-f48.google.com (mail-ee0-f48.google.com [74.125.83.48]) by gabe.freedesktop.org (Postfix) with ESMTP id 0ED7E6EC26 for ; Thu, 22 May 2014 07:35:37 -0700 (PDT) Received: by mail-ee0-f48.google.com with SMTP id e49so2706499eek.35 for ; Thu, 22 May 2014 07:35:37 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140520114645.4e04370f@jbarnes-desktop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, May 20, 2014 at 11:46:45AM -0700, Jesse Barnes wrote: > On Mon, 19 May 2014 19:23:27 +0300 > ville.syrjala@linux.intel.com wrote: > = > > From: Ville Syrj=E4l=E4 > > = > > Apparently we need to disable VCP unit clock gating around media reset > > on g4x. > > = > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > > drivers/gpu/drm/i915/intel_uncore.c | 36 +++++++++++++++++++++++++++++= ++++++- > > 2 files changed, 39 insertions(+), 1 deletion(-) > > = > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i91= 5_reg.h > > index 6522af4..543f23c 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -1724,6 +1724,10 @@ enum punit_power_well { > > #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) > > #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) > > #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) > > + > > +#define VDECCLK_GATE_D 0x620C /* g4x only */ > > +#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) > > + > > #define RAMCLK_GATE_D 0x6210 /* CRL only */ > > #define DEUC 0x6214 /* CRL only */ > > = > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915= /intel_uncore.c > > index cd0d6e2..67385a9 100644 > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > @@ -990,6 +990,36 @@ static int i965_do_reset(struct drm_device *dev) > > return 0; > > } > > = > > +static int g4x_do_reset(struct drm_device *dev) > > +{ > > + struct drm_i915_private *dev_priv =3D dev->dev_private; > > + int ret; > > + > > + pci_write_config_byte(dev->pdev, I965_GDRST, > > + GRDOM_RENDER | GRDOM_RESET_ENABLE); > > + ret =3D wait_for(i965_reset_complete(dev), 500); > > + if (ret) > > + return ret; > > + > > + /* WaVcpClkGateDisableForMediaReset:ctg,elk */ > > + I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK= _GATE_DISABLE); > > + POSTING_READ(VDECCLK_GATE_D); > > + > > + pci_write_config_byte(dev->pdev, I965_GDRST, > > + GRDOM_MEDIA | GRDOM_RESET_ENABLE); > > + ret =3D wait_for(i965_reset_complete(dev), 500); > > + if (ret) > > + return ret; > > + > > + /* WaVcpClkGateDisableForMediaReset:ctg,elk */ > > + I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOC= K_GATE_DISABLE); > > + POSTING_READ(VDECCLK_GATE_D); > > + > > + pci_write_config_byte(dev->pdev, I965_GDRST, 0); > > + > > + return 0; > > +} > > + > > static int ironlake_do_reset(struct drm_device *dev) > > { > > struct drm_i915_private *dev_priv =3D dev->dev_private; > > @@ -1042,7 +1072,11 @@ int intel_gpu_reset(struct drm_device *dev) > > case 7: > > case 6: return gen6_do_reset(dev); > > case 5: return ironlake_do_reset(dev); > > - case 4: return i965_do_reset(dev); > > + case 4: > > + if (IS_G4X(dev)) > > + return g4x_do_reset(dev); > > + else > > + return i965_do_reset(dev); > > default: return -ENODEV; > > } > > } > = > Given how the reset flow stuff works this seems sensible, but I > couldn't find it in the docs I have. Shouldn't do any harm at the very > worst... > = > Acked-by: Jesse Barnes I want the g4x/i965 split, so also merged this one here ;-) -Daniel -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch