From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 1/5] drm/i915: Add fifo underrun reporting state to debugfs
Date: Thu, 22 May 2014 20:02:53 +0300 [thread overview]
Message-ID: <20140522170253.GZ27580@intel.com> (raw)
In-Reply-To: <1400774195-19414-1-git-send-email-daniel.vetter@ffwll.ch>
On Thu, May 22, 2014 at 05:56:31PM +0200, Daniel Vetter wrote:
> On platforms with shared interrupt enable bits (which are shared even
> with the pipe CRC logic) there's some tricky corner cases. Add
> information to make debugging those easier.
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
For patches 1,3,4:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 16bbdc7243df..4a79d3fe35be 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2356,6 +2356,10 @@ static int i915_display_info(struct seq_file *m, void *unused)
> x, y, crtc->cursor_addr,
> yesno(active));
> }
> +
> + seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
> + yesno(!crtc->cpu_fifo_underrun_disabled),
> + yesno(!crtc->pch_fifo_underrun_disabled));
> }
>
> seq_printf(m, "\n");
> --
> 1.8.4.rc3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
prev parent reply other threads:[~2014-05-22 17:03 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-22 15:56 [PATCH 1/5] drm/i915: Add fifo underrun reporting state to debugfs Daniel Vetter
2014-05-22 15:56 ` [PATCH 2/5] drm/i915: Fix up fifo underrun tracking, take N Daniel Vetter
2014-05-22 16:55 ` Ville Syrjälä
2014-05-22 20:10 ` Daniel Vetter
2014-05-23 8:11 ` Ville Syrjälä
2014-05-23 8:21 ` Daniel Vetter
2014-05-26 8:09 ` Ville Syrjälä
2014-05-26 8:11 ` Daniel Vetter
2014-05-22 15:56 ` [PATCH 3/5] drm/i915: Disable gpu reset on i965g/gm Daniel Vetter
2014-05-22 15:56 ` [PATCH 4/5] drm/i915: Inline ilk/gen8_irq_reset Daniel Vetter
2014-05-22 15:56 ` [PATCH 5/5] drm/i915: Improve irq handling after gpu resets Daniel Vetter
2014-05-22 16:51 ` Ville Syrjälä
2014-05-22 17:06 ` Ville Syrjälä
2014-05-22 20:12 ` Daniel Vetter
2014-05-22 20:18 ` [PATCH 1/2] " Daniel Vetter
2014-05-22 20:18 ` [PATCH 2/2] drm/i915: Extract gen8_gt_irq_reset Daniel Vetter
2014-05-26 8:36 ` [PATCH 1/2] drm/i915: Improve irq handling after gpu resets Ville Syrjälä
2014-05-26 10:48 ` Daniel Vetter
2014-05-22 17:02 ` Ville Syrjälä [this message]
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