public inbox for intel-gfx@lists.freedesktop.org
 help / color / mirror / Atom feed
From: Daniel Vetter <daniel@ffwll.ch>
To: deepak.s@linux.intel.com
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/7] drm/i915/chv: Added CHV specific register read and write and Streamline CHV forcewake stuff
Date: Mon, 26 May 2014 10:07:00 +0200	[thread overview]
Message-ID: <20140526080700.GV14357@phenom.ffwll.local> (raw)
In-Reply-To: <1400859021-32202-3-git-send-email-deepak.s@linux.intel.com>

On Fri, May 23, 2014 at 09:00:16PM +0530, deepak.s@linux.intel.com wrote:
> From: Deepak S <deepak.s@linux.intel.com>
> 
> Support to individually control Media/Render well based on the register access.
> Add CHV specific write function to habdle difference between registers
> that are sadowed vs those that need forcewake even for writes.
> 
> Streamline the CHV forcewake functions just like was done for VLV.
> 
> This will also fix a bug in accessing the common well registers,
> where we'd end up trying to wake up the wells too many times
> since we'd call force_wake_get/put twice per register access, with
> FORCEFAKE_ALL both times.
> 
> v2: Drop write FIFO for CHV and add comman well forcewake (Ville)
>     Re-factor CHV/VLV Forcewake offsets (Ben)
> 
> v3: Fix for decrementing fw count in chv read/write. (Deepak)
> 
> v4: Squash the patches (Mika)
> 
> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
> [vsyrjala: Move the register range macros into intel_uncore.c]
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>

Only merged up to this one stil the next patch is missing r-b still. Mika?
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 135 +++++++++++++++++++++++++++++++-----
>  1 file changed, 118 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 2f5d5d3..7409de0 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -486,16 +486,43 @@ void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
>  #define NEEDS_FORCE_WAKE(dev_priv, reg) \
>  	 ((reg) < 0x40000 && (reg) != FORCEWAKE)
>  
> -#define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
> -	(((reg) >= 0x2000 && (reg) < 0x4000) ||\
> -	((reg) >= 0x5000 && (reg) < 0x8000) ||\
> -	((reg) >= 0xB000 && (reg) < 0x12000) ||\
> -	((reg) >= 0x2E000 && (reg) < 0x30000))
> +#define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
>  
> -#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\
> -	(((reg) >= 0x12000 && (reg) < 0x14000) ||\
> -	((reg) >= 0x22000 && (reg) < 0x24000) ||\
> -	((reg) >= 0x30000 && (reg) < 0x40000))
> +#define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
> +	(REG_RANGE((reg), 0x2000, 0x4000) || \
> +	 REG_RANGE((reg), 0x5000, 0x8000) || \
> +	 REG_RANGE((reg), 0xB000, 0x12000) || \
> +	 REG_RANGE((reg), 0x2E000, 0x30000))
> +
> +#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
> +	(REG_RANGE((reg), 0x12000, 0x14000) || \
> +	 REG_RANGE((reg), 0x22000, 0x24000) || \
> +	 REG_RANGE((reg), 0x30000, 0x40000))
> +
> +#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
> +	(REG_RANGE((reg), 0x2000, 0x4000) || \
> +	 REG_RANGE((reg), 0x5000, 0x8000) || \
> +	 REG_RANGE((reg), 0x8300, 0x8500) || \
> +	 REG_RANGE((reg), 0xB000, 0xC000) || \
> +	 REG_RANGE((reg), 0xE000, 0xE800))
> +
> +#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
> +	(REG_RANGE((reg), 0x8800, 0x8900) || \
> +	 REG_RANGE((reg), 0xD000, 0xD800) || \
> +	 REG_RANGE((reg), 0x12000, 0x14000) || \
> +	 REG_RANGE((reg), 0x1A000, 0x1C000) || \
> +	 REG_RANGE((reg), 0x1E800, 0x1EA00) || \
> +	 REG_RANGE((reg), 0x30000, 0x40000))
> +
> +#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
> +	(REG_RANGE((reg), 0x4000, 0x5000) || \
> +	 REG_RANGE((reg), 0x8000, 0x8300) || \
> +	 REG_RANGE((reg), 0x8500, 0x8600) || \
> +	 REG_RANGE((reg), 0x9000, 0xB000) || \
> +	 REG_RANGE((reg), 0xC000, 0xC800) || \
> +	 REG_RANGE((reg), 0xF000, 0x10000) || \
> +	 REG_RANGE((reg), 0x14000, 0x14400) || \
> +	 REG_RANGE((reg), 0x22000, 0x24000))
>  
>  static void
>  ilk_dummy_write(struct drm_i915_private *dev_priv)
> @@ -590,7 +617,35 @@ vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
>  	REG_READ_FOOTER; \
>  }
>  
> +#define __chv_read(x) \
> +static u##x \
> +chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
> +	unsigned fwengine = 0; \
> +	REG_READ_HEADER(x); \
> +	if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
> +		if (dev_priv->uncore.fw_rendercount == 0) \
> +			fwengine = FORCEWAKE_RENDER; \
> +	} else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
> +		if (dev_priv->uncore.fw_mediacount == 0) \
> +			fwengine = FORCEWAKE_MEDIA; \
> +	} else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
> +		if (dev_priv->uncore.fw_rendercount == 0) \
> +			fwengine |= FORCEWAKE_RENDER; \
> +		if (dev_priv->uncore.fw_mediacount == 0) \
> +			fwengine |= FORCEWAKE_MEDIA; \
> +	} \
> +	if (fwengine) \
> +		dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
> +	val = __raw_i915_read##x(dev_priv, reg); \
> +	if (fwengine) \
> +		dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
> +	REG_READ_FOOTER; \
> +}
>  
> +__chv_read(8)
> +__chv_read(16)
> +__chv_read(32)
> +__chv_read(64)
>  __vlv_read(8)
>  __vlv_read(16)
>  __vlv_read(32)
> @@ -608,6 +663,7 @@ __gen4_read(16)
>  __gen4_read(32)
>  __gen4_read(64)
>  
> +#undef __chv_read
>  #undef __vlv_read
>  #undef __gen6_read
>  #undef __gen5_read
> @@ -712,6 +768,38 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
>  	REG_WRITE_FOOTER; \
>  }
>  
> +#define __chv_write(x) \
> +static void \
> +chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
> +	unsigned fwengine = 0; \
> +	bool shadowed = is_gen8_shadowed(dev_priv, reg); \
> +	REG_WRITE_HEADER; \
> +	if (!shadowed) { \
> +		if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
> +			if (dev_priv->uncore.fw_rendercount == 0) \
> +				fwengine = FORCEWAKE_RENDER; \
> +		} else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
> +			if (dev_priv->uncore.fw_mediacount == 0) \
> +				fwengine = FORCEWAKE_MEDIA; \
> +		} else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
> +			if (dev_priv->uncore.fw_rendercount == 0) \
> +				fwengine |= FORCEWAKE_RENDER; \
> +			if (dev_priv->uncore.fw_mediacount == 0) \
> +				fwengine |= FORCEWAKE_MEDIA; \
> +		} \
> +	} \
> +	if (fwengine) \
> +		dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
> +	__raw_i915_write##x(dev_priv, reg, val); \
> +	if (fwengine) \
> +		dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
> +	REG_WRITE_FOOTER; \
> +}
> +
> +__chv_write(8)
> +__chv_write(16)
> +__chv_write(32)
> +__chv_write(64)
>  __gen8_write(8)
>  __gen8_write(16)
>  __gen8_write(32)
> @@ -733,6 +821,7 @@ __gen4_write(16)
>  __gen4_write(32)
>  __gen4_write(64)
>  
> +#undef __chv_write
>  #undef __gen8_write
>  #undef __hsw_write
>  #undef __gen6_write
> @@ -796,14 +885,26 @@ void intel_uncore_init(struct drm_device *dev)
>  
>  	switch (INTEL_INFO(dev)->gen) {
>  	default:
> -		dev_priv->uncore.funcs.mmio_writeb  = gen8_write8;
> -		dev_priv->uncore.funcs.mmio_writew  = gen8_write16;
> -		dev_priv->uncore.funcs.mmio_writel  = gen8_write32;
> -		dev_priv->uncore.funcs.mmio_writeq  = gen8_write64;
> -		dev_priv->uncore.funcs.mmio_readb  = gen6_read8;
> -		dev_priv->uncore.funcs.mmio_readw  = gen6_read16;
> -		dev_priv->uncore.funcs.mmio_readl  = gen6_read32;
> -		dev_priv->uncore.funcs.mmio_readq  = gen6_read64;
> +		if (IS_CHERRYVIEW(dev)) {
> +			dev_priv->uncore.funcs.mmio_writeb  = chv_write8;
> +			dev_priv->uncore.funcs.mmio_writew  = chv_write16;
> +			dev_priv->uncore.funcs.mmio_writel  = chv_write32;
> +			dev_priv->uncore.funcs.mmio_writeq  = chv_write64;
> +			dev_priv->uncore.funcs.mmio_readb  = chv_read8;
> +			dev_priv->uncore.funcs.mmio_readw  = chv_read16;
> +			dev_priv->uncore.funcs.mmio_readl  = chv_read32;
> +			dev_priv->uncore.funcs.mmio_readq  = chv_read64;
> +
> +		} else {
> +			dev_priv->uncore.funcs.mmio_writeb  = gen8_write8;
> +			dev_priv->uncore.funcs.mmio_writew  = gen8_write16;
> +			dev_priv->uncore.funcs.mmio_writel  = gen8_write32;
> +			dev_priv->uncore.funcs.mmio_writeq  = gen8_write64;
> +			dev_priv->uncore.funcs.mmio_readb  = gen6_read8;
> +			dev_priv->uncore.funcs.mmio_readw  = gen6_read16;
> +			dev_priv->uncore.funcs.mmio_readl  = gen6_read32;
> +			dev_priv->uncore.funcs.mmio_readq  = gen6_read64;
> +		}
>  		break;
>  	case 7:
>  	case 6:
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

  reply	other threads:[~2014-05-26  8:07 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-05-23 15:30 [PATCH 0/7] Enable RC6/Turbo on CHV deepak.s
2014-05-23 15:30 ` [PATCH 1/7] drm/i915/chv: Enable Render Standby (RC6) for Cherryview deepak.s
2014-05-23 15:30 ` [PATCH 2/7] drm/i915/chv: Added CHV specific register read and write and Streamline CHV forcewake stuff deepak.s
2014-05-26  8:07   ` Daniel Vetter [this message]
2014-05-23 15:30 ` [PATCH 3/7] drm/i915/chv: Enable RPS (Turbo) for Cherryview deepak.s
2014-05-26 13:30   ` Mika Kuoppala
2014-05-26 13:54     ` Deepak S
2014-05-26 14:32       ` Ville Syrjälä
2014-05-27  3:29         ` Deepak S
2014-05-26 14:37       ` Mika Kuoppala
2014-05-27  3:29         ` Deepak S
2014-05-27  6:36       ` [PATCH v6] " deepak.s
2014-05-27 10:29       ` [PATCH v7] " deepak.s
2014-05-27 10:45         ` Mika Kuoppala
2014-05-27 11:44           ` Daniel Vetter
2014-05-23 15:30 ` [PATCH 4/7] drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0 deepak.s
2014-05-23 15:30 ` [PATCH 5/7] drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV deepak.s
2014-05-23 15:30 ` [PATCH 6/7] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating deepak.s
2014-05-26 15:19   ` Mika Kuoppala
2014-05-27 11:42     ` Daniel Vetter
2014-05-27 11:59       ` Ville Syrjälä
2014-05-27 12:11         ` Deepak S
2014-05-27 12:13       ` Deepak S
2014-05-23 15:30 ` [PATCH 7/7] drm/i915/chv: Freq(opcode) request for CHV deepak.s

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20140526080700.GV14357@phenom.ffwll.local \
    --to=daniel@ffwll.ch \
    --cc=deepak.s@linux.intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox