From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 2/7] drm/i915/chv: Added CHV specific register read and write and Streamline CHV forcewake stuff Date: Mon, 26 May 2014 10:07:00 +0200 Message-ID: <20140526080700.GV14357@phenom.ffwll.local> References: <1400859021-32202-1-git-send-email-deepak.s@linux.intel.com> <1400859021-32202-3-git-send-email-deepak.s@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-wg0-f46.google.com (mail-wg0-f46.google.com [74.125.82.46]) by gabe.freedesktop.org (Postfix) with ESMTP id 1CF676E154 for ; Mon, 26 May 2014 01:07:04 -0700 (PDT) Received: by mail-wg0-f46.google.com with SMTP id n12so7616973wgh.29 for ; Mon, 26 May 2014 01:07:03 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1400859021-32202-3-git-send-email-deepak.s@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: deepak.s@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, May 23, 2014 at 09:00:16PM +0530, deepak.s@linux.intel.com wrote: > From: Deepak S > = > Support to individually control Media/Render well based on the register a= ccess. > Add CHV specific write function to habdle difference between registers > that are sadowed vs those that need forcewake even for writes. > = > Streamline the CHV forcewake functions just like was done for VLV. > = > This will also fix a bug in accessing the common well registers, > where we'd end up trying to wake up the wells too many times > since we'd call force_wake_get/put twice per register access, with > FORCEFAKE_ALL both times. > = > v2: Drop write FIFO for CHV and add comman well forcewake (Ville) > Re-factor CHV/VLV Forcewake offsets (Ben) > = > v3: Fix for decrementing fw count in chv read/write. (Deepak) > = > v4: Squash the patches (Mika) > = > Reviewed-by: Mika Kuoppala > [vsyrjala: Move the register range macros into intel_uncore.c] > Signed-off-by: Ville Syrj=E4l=E4 > Signed-off-by: Deepak S Only merged up to this one stil the next patch is missing r-b still. Mika? -Daniel > --- > drivers/gpu/drm/i915/intel_uncore.c | 135 ++++++++++++++++++++++++++++++= +----- > 1 file changed, 118 insertions(+), 17 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/i= ntel_uncore.c > index 2f5d5d3..7409de0 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -486,16 +486,43 @@ void assert_force_wake_inactive(struct drm_i915_pri= vate *dev_priv) > #define NEEDS_FORCE_WAKE(dev_priv, reg) \ > ((reg) < 0x40000 && (reg) !=3D FORCEWAKE) > = > -#define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \ > - (((reg) >=3D 0x2000 && (reg) < 0x4000) ||\ > - ((reg) >=3D 0x5000 && (reg) < 0x8000) ||\ > - ((reg) >=3D 0xB000 && (reg) < 0x12000) ||\ > - ((reg) >=3D 0x2E000 && (reg) < 0x30000)) > +#define REG_RANGE(reg, start, end) ((reg) >=3D (start) && (reg) < (end)) > = > -#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\ > - (((reg) >=3D 0x12000 && (reg) < 0x14000) ||\ > - ((reg) >=3D 0x22000 && (reg) < 0x24000) ||\ > - ((reg) >=3D 0x30000 && (reg) < 0x40000)) > +#define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \ > + (REG_RANGE((reg), 0x2000, 0x4000) || \ > + REG_RANGE((reg), 0x5000, 0x8000) || \ > + REG_RANGE((reg), 0xB000, 0x12000) || \ > + REG_RANGE((reg), 0x2E000, 0x30000)) > + > +#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \ > + (REG_RANGE((reg), 0x12000, 0x14000) || \ > + REG_RANGE((reg), 0x22000, 0x24000) || \ > + REG_RANGE((reg), 0x30000, 0x40000)) > + > +#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \ > + (REG_RANGE((reg), 0x2000, 0x4000) || \ > + REG_RANGE((reg), 0x5000, 0x8000) || \ > + REG_RANGE((reg), 0x8300, 0x8500) || \ > + REG_RANGE((reg), 0xB000, 0xC000) || \ > + REG_RANGE((reg), 0xE000, 0xE800)) > + > +#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \ > + (REG_RANGE((reg), 0x8800, 0x8900) || \ > + REG_RANGE((reg), 0xD000, 0xD800) || \ > + REG_RANGE((reg), 0x12000, 0x14000) || \ > + REG_RANGE((reg), 0x1A000, 0x1C000) || \ > + REG_RANGE((reg), 0x1E800, 0x1EA00) || \ > + REG_RANGE((reg), 0x30000, 0x40000)) > + > +#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \ > + (REG_RANGE((reg), 0x4000, 0x5000) || \ > + REG_RANGE((reg), 0x8000, 0x8300) || \ > + REG_RANGE((reg), 0x8500, 0x8600) || \ > + REG_RANGE((reg), 0x9000, 0xB000) || \ > + REG_RANGE((reg), 0xC000, 0xC800) || \ > + REG_RANGE((reg), 0xF000, 0x10000) || \ > + REG_RANGE((reg), 0x14000, 0x14400) || \ > + REG_RANGE((reg), 0x22000, 0x24000)) > = > static void > ilk_dummy_write(struct drm_i915_private *dev_priv) > @@ -590,7 +617,35 @@ vlv_read##x(struct drm_i915_private *dev_priv, off_t= reg, bool trace) { \ > REG_READ_FOOTER; \ > } > = > +#define __chv_read(x) \ > +static u##x \ > +chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ > + unsigned fwengine =3D 0; \ > + REG_READ_HEADER(x); \ > + if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \ > + if (dev_priv->uncore.fw_rendercount =3D=3D 0) \ > + fwengine =3D FORCEWAKE_RENDER; \ > + } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ > + if (dev_priv->uncore.fw_mediacount =3D=3D 0) \ > + fwengine =3D FORCEWAKE_MEDIA; \ > + } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \ > + if (dev_priv->uncore.fw_rendercount =3D=3D 0) \ > + fwengine |=3D FORCEWAKE_RENDER; \ > + if (dev_priv->uncore.fw_mediacount =3D=3D 0) \ > + fwengine |=3D FORCEWAKE_MEDIA; \ > + } \ > + if (fwengine) \ > + dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ > + val =3D __raw_i915_read##x(dev_priv, reg); \ > + if (fwengine) \ > + dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ > + REG_READ_FOOTER; \ > +} > = > +__chv_read(8) > +__chv_read(16) > +__chv_read(32) > +__chv_read(64) > __vlv_read(8) > __vlv_read(16) > __vlv_read(32) > @@ -608,6 +663,7 @@ __gen4_read(16) > __gen4_read(32) > __gen4_read(64) > = > +#undef __chv_read > #undef __vlv_read > #undef __gen6_read > #undef __gen5_read > @@ -712,6 +768,38 @@ gen8_write##x(struct drm_i915_private *dev_priv, off= _t reg, u##x val, bool trace > REG_WRITE_FOOTER; \ > } > = > +#define __chv_write(x) \ > +static void \ > +chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, boo= l trace) { \ > + unsigned fwengine =3D 0; \ > + bool shadowed =3D is_gen8_shadowed(dev_priv, reg); \ > + REG_WRITE_HEADER; \ > + if (!shadowed) { \ > + if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \ > + if (dev_priv->uncore.fw_rendercount =3D=3D 0) \ > + fwengine =3D FORCEWAKE_RENDER; \ > + } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ > + if (dev_priv->uncore.fw_mediacount =3D=3D 0) \ > + fwengine =3D FORCEWAKE_MEDIA; \ > + } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \ > + if (dev_priv->uncore.fw_rendercount =3D=3D 0) \ > + fwengine |=3D FORCEWAKE_RENDER; \ > + if (dev_priv->uncore.fw_mediacount =3D=3D 0) \ > + fwengine |=3D FORCEWAKE_MEDIA; \ > + } \ > + } \ > + if (fwengine) \ > + dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ > + __raw_i915_write##x(dev_priv, reg, val); \ > + if (fwengine) \ > + dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ > + REG_WRITE_FOOTER; \ > +} > + > +__chv_write(8) > +__chv_write(16) > +__chv_write(32) > +__chv_write(64) > __gen8_write(8) > __gen8_write(16) > __gen8_write(32) > @@ -733,6 +821,7 @@ __gen4_write(16) > __gen4_write(32) > __gen4_write(64) > = > +#undef __chv_write > #undef __gen8_write > #undef __hsw_write > #undef __gen6_write > @@ -796,14 +885,26 @@ void intel_uncore_init(struct drm_device *dev) > = > switch (INTEL_INFO(dev)->gen) { > default: > - dev_priv->uncore.funcs.mmio_writeb =3D gen8_write8; > - dev_priv->uncore.funcs.mmio_writew =3D gen8_write16; > - dev_priv->uncore.funcs.mmio_writel =3D gen8_write32; > - dev_priv->uncore.funcs.mmio_writeq =3D gen8_write64; > - dev_priv->uncore.funcs.mmio_readb =3D gen6_read8; > - dev_priv->uncore.funcs.mmio_readw =3D gen6_read16; > - dev_priv->uncore.funcs.mmio_readl =3D gen6_read32; > - dev_priv->uncore.funcs.mmio_readq =3D gen6_read64; > + if (IS_CHERRYVIEW(dev)) { > + dev_priv->uncore.funcs.mmio_writeb =3D chv_write8; > + dev_priv->uncore.funcs.mmio_writew =3D chv_write16; > + dev_priv->uncore.funcs.mmio_writel =3D chv_write32; > + dev_priv->uncore.funcs.mmio_writeq =3D chv_write64; > + dev_priv->uncore.funcs.mmio_readb =3D chv_read8; > + dev_priv->uncore.funcs.mmio_readw =3D chv_read16; > + dev_priv->uncore.funcs.mmio_readl =3D chv_read32; > + dev_priv->uncore.funcs.mmio_readq =3D chv_read64; > + > + } else { > + dev_priv->uncore.funcs.mmio_writeb =3D gen8_write8; > + dev_priv->uncore.funcs.mmio_writew =3D gen8_write16; > + dev_priv->uncore.funcs.mmio_writel =3D gen8_write32; > + dev_priv->uncore.funcs.mmio_writeq =3D gen8_write64; > + dev_priv->uncore.funcs.mmio_readb =3D gen6_read8; > + dev_priv->uncore.funcs.mmio_readw =3D gen6_read16; > + dev_priv->uncore.funcs.mmio_readl =3D gen6_read32; > + dev_priv->uncore.funcs.mmio_readq =3D gen6_read64; > + } > break; > case 7: > case 6: > -- = > 1.9.1 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch