From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 6/7] drm/i915/chv: Added CHV specific DDR fetch into init_clock_gating Date: Tue, 27 May 2014 13:42:50 +0200 Message-ID: <20140527114250.GI14357@phenom.ffwll.local> References: <1400859021-32202-1-git-send-email-deepak.s@linux.intel.com> <1400859021-32202-7-git-send-email-deepak.s@linux.intel.com> <877g58sh3o.fsf@gaia.fi.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-wi0-f181.google.com (mail-wi0-f181.google.com [209.85.212.181]) by gabe.freedesktop.org (Postfix) with ESMTP id A98356E66A for ; Tue, 27 May 2014 04:42:54 -0700 (PDT) Received: by mail-wi0-f181.google.com with SMTP id n15so1523656wiw.14 for ; Tue, 27 May 2014 04:42:53 -0700 (PDT) Content-Disposition: inline In-Reply-To: <877g58sh3o.fsf@gaia.fi.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Mika Kuoppala Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, May 26, 2014 at 06:19:07PM +0300, Mika Kuoppala wrote: > deepak.s@linux.intel.com writes: > = > > From: Deepak S > > > > Signed-off-by: Deepak S > > [vsyrjala: Fix merge fubmle where the code ended up in > > g4x_disable_trickle_feed() instead of cherryview_init_clock_gating()] > > Signed-off-by: Ville Syrj=E4l=E4 > > Acked-by: Ben Widawsky > > --- > > drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++ > > 1 file changed, 11 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > > index 08dcdc5..0b73a6d 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -4026,7 +4026,18 @@ static void cherryview_enable_rps(struct drm_dev= ice *dev) > > GEN6_RP_UP_BUSY_AVG | > > GEN6_RP_DOWN_IDLE_AVG); > > = > > + /* ToDo: Update the mem freq based on latest spec [CHV]*/ > = > Please do and consider fixing the vlv decoding. It seems to be off > too. Poke about this one here. Iirc the situation on vlv is simply terminal confusion, and iirc the current code matches reality of shipping vbiosen, but not any spec. I hope we're bettter for chv. -Daniel > = > -Mika > = > > val =3D vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); > > + switch ((val >> 6) & 3) { > > + case 0: > > + case 1: > > + case 2: > > + dev_priv->mem_freq =3D 1600; > > + break; > > + case 3: > > + dev_priv->mem_freq =3D 2000; > > + break; > > + } > > = > > DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); > > DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); > > -- = > > 1.9.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch