From mboxrd@z Thu Jan 1 00:00:00 1970 From: Damien Lespiau Subject: Re: [PATCH v2 6/6] drm/i915/vlv: Modifying WA 'WaDisableL3Bank2xClockGate for vlv Date: Tue, 27 May 2014 15:27:23 +0100 Message-ID: <20140527142723.GA27337@strange.amr.corp.intel.com> References: <1395682207-7092-1-git-send-email-sourab.gupta@intel.com> <1395682207-7092-7-git-send-email-sourab.gupta@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 254896E43A for ; Tue, 27 May 2014 07:27:26 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1395682207-7092-7-git-send-email-sourab.gupta@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: sourab.gupta@intel.com Cc: Daniel Vetter , intel-gfx@lists.freedesktop.org, Akash Goel List-Id: intel-gfx@lists.freedesktop.org On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gupta@intel.com wrote: > From: Akash Goel > > For disabling L3 clock gating we need to set bit 25 of MMIO > register 940c. Earlier this was being done by just writing 1 > into bit 25 and resetting all other bits. > This patch modifies the routine to read-modify-write of the > register, so that the values of other bits are not destroyed. > > v2: Modifying the comments and the patch commit message (Chris) > > Signed-off-by: Akash Goel > Signed-off-by: Sourab Gupta Apart from the multiline comment format and the second line not aligned with the '(' as we usually do: Reviewed-by: Damien Lespiau -- Damien > --- > drivers/gpu/drm/i915/intel_pm.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index c3a8554..af4bb8e 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5093,8 +5093,11 @@ static void valleyview_init_clock_gating(struct drm_device *dev) > I915_WRITE(GEN6_UCGCTL2, > GEN6_RCZUNIT_CLOCK_GATE_DISABLE); > > - /* WaDisableL3Bank2xClockGate:vlv */ > - I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); > + /* WaDisableL3Bank2xClockGate:vlv > + * Disabling L3 clock gating- MMIO 940c[25] = 1 > + * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ > + I915_WRITE(GEN7_UCGCTL4, > + I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); > > I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); > > -- > 1.8.5.1 >