From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH v2 6/6] drm/i915/vlv: Modifying WA
 'WaDisableL3Bank2xClockGate for vlv
Date: Tue, 27 May 2014 18:54:33 +0200
Message-ID: <20140527165433.GC14841@phenom.ffwll.local>
References: <1395682207-7092-1-git-send-email-sourab.gupta@intel.com>
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To: Damien Lespiau <damien.lespiau@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>, intel-gfx@lists.freedesktop.org, sourab.gupta@intel.com, Akash Goel <akash.goel@intel.com>
List-Id: intel-gfx@lists.freedesktop.org

On Tue, May 27, 2014 at 03:27:23PM +0100, Damien Lespiau wrote:
> On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gupta@intel.com wrote:
> > From: Akash Goel <akash.goel@intel.com>
> > 
> > For disabling L3 clock gating we need to set bit 25 of MMIO
> > register 940c. Earlier this was being done by just writing 1
> > into bit 25 and resetting all other bits.
> > This patch modifies the routine to read-modify-write of the
> > register, so that the values of other bits are not destroyed.
> > 
> > v2: Modifying the comments and the patch commit message (Chris)
> > 
> > Signed-off-by: Akash Goel <akash.goel@intel.com>
> > Signed-off-by: Sourab Gupta <sourab.gupta@intel.com>
> 
> Apart from the multiline comment format and the second line not aligned
> with the '(' as we usually do:

Fixed.

> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch