From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 1/2] drm/i915: Replaced Blitter ring based
 flips with MMIO flips
Date: Wed, 28 May 2014 11:12:50 +0300
Message-ID: <20140528081250.GQ27580@intel.com>
References: <20140527130919.GB14841@phenom.ffwll.local>
 <1401261122-23593-1-git-send-email-sourab.gupta@intel.com>
 <1401261122-23593-2-git-send-email-sourab.gupta@intel.com>
 <20140528073152.GD18409@nuc-i3427.alporthouse.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Return-path: <intel-gfx-bounces@lists.freedesktop.org>
Received: from mga09.intel.com (mga09.intel.com [134.134.136.24])
 by gabe.freedesktop.org (Postfix) with ESMTP id 24BCF6E4FF
 for <intel-gfx@lists.freedesktop.org>; Wed, 28 May 2014 01:13:05 -0700 (PDT)
Content-Disposition: inline
In-Reply-To: <20140528073152.GD18409@nuc-i3427.alporthouse.com>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
 <mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
 <mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Errors-To: intel-gfx-bounces@lists.freedesktop.org
Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
To: Chris Wilson <chris@chris-wilson.co.uk>, sourab.gupta@intel.com, intel-gfx@lists.freedesktop.org, Deepak S <deepak.s@intel.com>, Akash Goel <akash.goel@intel.com>
List-Id: intel-gfx@lists.freedesktop.org

On Wed, May 28, 2014 at 08:31:52AM +0100, Chris Wilson wrote:
> On Wed, May 28, 2014 at 12:42:01PM +0530, sourab.gupta@intel.com wrote:
> > +static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
> > +{
> > +	struct drm_device *dev =3D intel_crtc->base.dev;
> > +	struct drm_i915_private *dev_priv =3D dev->dev_private;
> > +	struct intel_framebuffer *intel_fb =3D
> > +		to_intel_framebuffer(intel_crtc->base.primary->fb);
> > +	struct drm_i915_gem_object *obj =3D intel_fb->obj;
> > +	u32 dspcntr;
> > +	u32 reg;
> > +
> > +	intel_mark_page_flip_active(intel_crtc);
> > +
> > +	reg =3D DSPCNTR(intel_crtc->plane);
> > +	dspcntr =3D I915_READ(reg);
> > +
> > +	if (INTEL_INFO(dev)->gen >=3D 4) {
> > +		if (obj->tiling_mode !=3D I915_TILING_NONE)
> > +			dspcntr |=3D DISPPLANE_TILED;
> > +		else
> > +			dspcntr &=3D ~DISPPLANE_TILED;
> > +	}
> > +	I915_WRITE(reg, dspcntr);
> > +
> > +	I915_WRITE(DSPSURF(intel_crtc->plane),
> > +			intel_crtc->unpin_work->gtt_offset);
> > +	POSTING_READ(DSPSURF(intel_crtc->plane));
> > +}
> =

> So other than byt, why would we not use LRI here and avoid waking the
> CPU up?

The plan is to eventually expand this thing to handle the nuclear flip
and we're going use mmio for that. So going for mmio from the start
seems fine to me. Especially since we need the mmio path for byt anyway.

-- =

Ville Syrj=E4l=E4
Intel OTC