From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 66/66] drm/i915: runtime PM support for DPMS Date: Mon, 2 Jun 2014 18:09:38 +0200 Message-ID: <20140602160937.GD19050@phenom.ffwll.local> References: <1398376542-27825-1-git-send-email-daniel.vetter@ffwll.ch> <1398376542-27825-67-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wi0-f176.google.com (mail-wi0-f176.google.com [209.85.212.176]) by gabe.freedesktop.org (Postfix) with ESMTP id 5B0086E5F4 for ; Mon, 2 Jun 2014 09:09:44 -0700 (PDT) Received: by mail-wi0-f176.google.com with SMTP id n15so4832320wiw.9 for ; Mon, 02 Jun 2014 09:09:43 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1398376542-27825-67-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Intel Graphics Development Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org On Thu, Apr 24, 2014 at 11:55:42PM +0200, Daniel Vetter wrote: > Keeping track of the power domains is a bit messy since crtc->active > is currently updated by the platform hooks, but we need to be aware of > which state transition exactly is going on. Maybe we simply need to > shovel all the power domain handling down into platform code to > simplify this. But doing that requires some more auditing since > currently the ->mode_set callbacks still read some random registers > (to e.g. figure out the reference clocks). > > Also note that intel_crtc_update_dpms is always call first/last even > for encoders which have their own dpms functions. Hence we really only > need to update this place here. > > Being a quick "does it blow up?" run not really tested yet. > > Signed-off-by: Daniel Vetter Ok, I've simply gone ahead and merged this with a !HAS_DDI check so that I can unblock runtime pm for dpms. -Daniel > --- > drivers/gpu/drm/i915/intel_display.c | 26 ++++++++++++++++++++++---- > 1 file changed, 22 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index e0bd0f94e43e..1b5d6b099b37 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4478,16 +4478,34 @@ void intel_crtc_update_dpms(struct drm_crtc *crtc) > { > struct drm_device *dev = crtc->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > struct intel_encoder *intel_encoder; > + enum intel_display_power_domain domain; > + unsigned long domains; > bool enable = false; > > for_each_encoder_on_crtc(dev, crtc, intel_encoder) > enable |= intel_encoder->connectors_active; > > - if (enable) > - dev_priv->display.crtc_enable(crtc); > - else > - dev_priv->display.crtc_disable(crtc); > + if (enable) { > + if (!intel_crtc->active) { > + domains = get_crtc_power_domains(crtc); > + for_each_power_domain(domain, domains) > + intel_display_power_get(dev_priv, domain); > + intel_crtc->enabled_power_domains = domains; > + > + dev_priv->display.crtc_enable(crtc); > + } > + } else { > + if (intel_crtc->active) { > + dev_priv->display.crtc_disable(crtc); > + > + domains = intel_crtc->enabled_power_domains; > + for_each_power_domain(domain, domains) > + intel_display_power_put(dev_priv, domain); > + intel_crtc->enabled_power_domains = 0; > + } > + } > > intel_crtc_update_sarea(crtc, enable); > } > -- > 1.8.1.4 > -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch