From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH] drm/i915: cache hw power well enabled state
Date: Fri, 6 Jun 2014 20:05:43 +0200
Message-ID: <20140606180543.GT7416@phenom.ffwll.local>
References: <20140528111708.253e2578@jbarnes-desktop>
 <1401989507-9290-1-git-send-email-imre.deak@intel.com>
 <20140606171904.GN7416@phenom.ffwll.local>
 <1402076268.3099.6.camel@ideak-mobl>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <intel-gfx-bounces@lists.freedesktop.org>
Received: from mail-wi0-f169.google.com (mail-wi0-f169.google.com
 [209.85.212.169])
 by gabe.freedesktop.org (Postfix) with ESMTP id 8DA666EAAD
 for <intel-gfx@lists.freedesktop.org>; Fri,  6 Jun 2014 11:05:49 -0700 (PDT)
Received: by mail-wi0-f169.google.com with SMTP id ho1so1318030wib.4
 for <intel-gfx@lists.freedesktop.org>; Fri, 06 Jun 2014 11:05:48 -0700 (PDT)
Content-Disposition: inline
In-Reply-To: <1402076268.3099.6.camel@ideak-mobl>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
 <mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
 <mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Errors-To: intel-gfx-bounces@lists.freedesktop.org
Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Fri, Jun 06, 2014 at 08:37:48PM +0300, Imre Deak wrote:
> On Fri, 2014-06-06 at 19:19 +0200, Daniel Vetter wrote:
> > On Thu, Jun 05, 2014 at 08:31:47PM +0300, Imre Deak wrote:
> > > Jesse noticed that the punit communication needed to query the VLV power
> > > well status can cause substantial delays. Since we can query the state
> > > frequently, for example during I2C transfers, maintain a cached version
> > > of the HW state to get rid of this delay.
> > > 
> > > This fixes at least one reported regression where boot time increased by
> > > ~4 seconds due to frequent power well state queries on VLV during eDP
> > > EDID read.
> > > 
> > > Reported-by: Jesse Barnes <jesse.barnes@intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > 
> > A citation for the regressing commit here (i.e. the one that enabled vlv
> > runtime pm) would be good so that Jani can pick it up.
> 
> I'm not aware of any other case where we had a significant overhead, so
> for the above particular issue I'd say
> 
> this was introduced by
> 
> commit bb4932c4f17b68f34645ffbcf845e4c29d17290b
> Author: Imre Deak <imre.deak@intel.com>
> Date:   Mon Apr 14 20:24:33 2014 +0300
> 
>     drm/i915: vlv: check port power domain instead of only D0 for eDP
> VDD on
> 
> > Aside: intel_rpm.c with the runtime pm infrastructure + some overview
> > kerneldoc would be really, really nice.
> 
> You mean to move out the power well and rpm stuff to this new file?
> Agreed, intel_pm.c is rather big already.

Well moving it out alone isn't that useful, but using that chance to add a
bit of documentation for the main functions and an overview would be
really good.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch