From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915: Fix VLV CRC reading. Date: Mon, 9 Jun 2014 14:42:41 +0300 Message-ID: <20140609114241.GO27580@intel.com> References: <1402003697-1671-1-git-send-email-rodrigo.vivi@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 183BF89518 for ; Mon, 9 Jun 2014 04:42:46 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1402003697-1671-1-git-send-email-rodrigo.vivi@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Rodrigo Vivi Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Jun 05, 2014 at 02:28:17PM -0700, Rodrigo Vivi wrote: > Adding missing Display mmio reg offset. > = > Credits-to: Laws, Philip > Cc: He, Shuang > Signed-off-by: Rodrigo Vivi Reviewed-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > = > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 286f05c..05e2541 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2627,7 +2627,7 @@ enum punit_power_well { > = > #define PORT_DFT_I9XX 0x61150 > #define DC_BALANCE_RESET (1 << 25) > -#define PORT_DFT2_G4X 0x61154 > +#define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154) > #define DC_BALANCE_RESET_VLV (1 << 31) > #define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0) > #define PIPE_B_SCRAMBLE_RESET (1 << 1) > -- = > 1.9.3 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC