From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915: Init important ns2501 registers Date: Tue, 10 Jun 2014 17:04:30 +0300 Message-ID: <20140610140430.GD27580@intel.com> References: <5395FFD4.9010302@math.tu-berlin.de> <28223_1402343538_53961072_28223_7661_1_1402343204-28608-1-git-send-email-ville.syrjala@linux.intel.com> <53963540.9000304@math.tu-berlin.de> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 7FB436E6AC for ; Tue, 10 Jun 2014 07:05:05 -0700 (PDT) Content-Disposition: inline In-Reply-To: <53963540.9000304@math.tu-berlin.de> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Thomas Richter Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Jun 10, 2014 at 12:29:20AM +0200, Thomas Richter wrote: > Hi Ville, > = > thanks for the latest patch. As said, the screen did not come back quite = > correctly. I checked the register values > again, and I am sorry to say that I was wrong - register values do = > differ. Apparently, the code configures now > the wrong pipe to generate output to the DVO and thus the DVO does not = > seem to synchronize correctly > anymore. Please find the two register dumps attached. Either pipe can drive DVO just fine. Looks like it's using pipe A in your register dump, and all the registers look fine to me. Well, DPLL B VCO enable is off since we don't currently have a mechanism to kick pipe B into action during resume/load. In theory that would need to be enabled as well. Can you see if a simple 'intel_reg_write 0x6018 0xc08b0000' fixes the problem? And if not, I'd like to see a diff of register dumps between working and non working setups. -- = Ville Syrj=E4l=E4 Intel OTC