From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: DevSNB PCI Config Space Registers Reference Date: Wed, 11 Jun 2014 12:19:44 +0200 Message-ID: <20140611101944.GG5821@phenom.ffwll.local> References: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wi0-f181.google.com (mail-wi0-f181.google.com [209.85.212.181]) by gabe.freedesktop.org (Postfix) with ESMTP id 17DFA6E81A for ; Wed, 11 Jun 2014 03:19:53 -0700 (PDT) Received: by mail-wi0-f181.google.com with SMTP id n3so798617wiv.2 for ; Wed, 11 Jun 2014 03:19:53 -0700 (PDT) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Nicolae Badiu Cc: "intel-gfx@lists.freedesktop.org" List-Id: intel-gfx@lists.freedesktop.org On Tue, Jun 10, 2014 at 03:51:03PM +0000, Nicolae Badiu wrote: > Hi, > > Does anyone have access to the Sandy Bridge 2011 Intel HD Graphics PCI > Config space register reference? I cannot seem to find it anywhere in > the PRM docs. There is only a reference to a register called MMAPA at > office 14h in all DevSNB manuals. > > I do see PCI config space documentation for Ivy Bridge and Haswell Intel HD Graphics. Yeah, this was missed in the snb release. > Otherwise, pointing me in the right direction w/ regard to the drm-intel source code would also help. They are sprinkled all over a bit, and we definitely don't have an exhaustive set of #defines. If you need something specific and interpolation with ivb/hsw docs doesn't work, please just ping us. Usually best on irc. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch