From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915/chv: Fix "drm/i915/chv: Add a bunch of pre production workarounds" Date: Thu, 12 Jun 2014 11:20:36 +0300 Message-ID: <20140612082036.GP27580@intel.com> References: <411E5DC12A51ED4CB1159E14310E532B9D8C3FC4@FMSMSX119.amr.corp.intel.com> <1402442794-166797-1-git-send-email-Tom.O'Rourke@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 66AD36E47D for ; Thu, 12 Jun 2014 01:21:12 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1402442794-166797-1-git-send-email-Tom.O'Rourke@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Tom.O'Rourke@intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Jun 10, 2014 at 04:26:34PM -0700, Tom.O'Rourke@intel.com wrote: > From: Tom O'Rourke > = > Correct a merge mishap in commit e4443e459ccf43f2c139358400365fd6a839d40d. > = > Wa*:chv belongs in cherryview_enable_rps, not gen8_enable_rps. > = > Signed-off-by: Tom O'Rourke Reviewed-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/intel_pm.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 18f0ba0..c6e893b 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3520,15 +3520,11 @@ static void gen8_enable_rps(struct drm_device *de= v) > = > I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); > = > - /* WaDisablePwrmtrEvent:chv (pre-production hw) */ > - I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff); > - I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00); > - > /* 5: Enable RPS */ > I915_WRITE(GEN6_RP_CONTROL, > GEN6_RP_MEDIA_TURBO | > GEN6_RP_MEDIA_HW_NORMAL_MODE | > - GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-producti= on hw ?) */ > + GEN6_RP_MEDIA_IS_GFX | > GEN6_RP_ENABLE | > GEN6_RP_UP_BUSY_AVG | > GEN6_RP_DOWN_IDLE_AVG); > @@ -4022,10 +4018,14 @@ static void cherryview_enable_rps(struct drm_devi= ce *dev) > = > I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); > = > + /* WaDisablePwrmtrEvent:chv (pre-production hw) */ > + I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff); > + I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00); > + > /* 5: Enable RPS */ > I915_WRITE(GEN6_RP_CONTROL, > GEN6_RP_MEDIA_HW_NORMAL_MODE | > - GEN6_RP_MEDIA_IS_GFX | > + GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-producti= on hw ?) */ > GEN6_RP_ENABLE | > GEN6_RP_UP_BUSY_AVG | > GEN6_RP_DOWN_IDLE_AVG); > -- = > 1.7.9.5 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC