From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [Intel-gfx] [PATCH] drm/i915: Don't take fp 0/1 selector into account for pll state Date: Mon, 16 Jun 2014 11:32:39 +0300 Message-ID: <20140616083239.GG27580@intel.com> References: <1402836942-31319-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Content-Disposition: inline In-Reply-To: <1402836942-31319-1-git-send-email-daniel.vetter@ffwll.ch> Sender: stable-owner@vger.kernel.org To: Daniel Vetter Cc: Intel Graphics Development , Aleks , stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org On Sun, Jun 15, 2014 at 02:55:42PM +0200, Daniel Vetter wrote: > It changes at runtime and so should be ignored for pipe state checks. > Note that we don't yet read out the full DRRS state, so there's some > gaps. Bu DRRS is also not yet enabled for LVDS by default. >=20 > Cc: Aleks > Reported-by: Aleks > Cc: stable@vger.kernel.org > Signed-off-by: Daniel Vetter > --- > drivers/gpu/drm/i915/intel_display.c | 3 +++ > 1 file changed, 3 insertions(+) >=20 > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i= 915/intel_display.c > index ba1d9aac3958..1ccf660e67d9 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -8549,6 +8549,9 @@ static void i9xx_crtc_clock_get(struct intel_cr= tc *crtc, > else > fp =3D pipe_config->dpll_hw_state.fp1; > =20 > + /* We don't compute the FPA 0/1 selector. */ > + dpll &=3D ~DISPLAY_RATE_SELECT_FPA1; > + But we still compute port_clock based on the currently active FPA register. Won't that make the clock checks fail as well? > clock.m1 =3D (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; > if (IS_PINEVIEW(dev)) { > clock.n =3D ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) -= 1; > --=20 > 2.0.0 >=20 > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx --=20 Ville Syrj=E4l=E4 Intel OTC