From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: Don't take fp 0/1 selector into account for pll state Date: Mon, 16 Jun 2014 20:01:26 +0200 Message-ID: <20140616180125.GD5821@phenom.ffwll.local> References: <1402836942-31319-1-git-send-email-daniel.vetter@ffwll.ch> <20140616083239.GG27580@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-wg0-f52.google.com (mail-wg0-f52.google.com [74.125.82.52]) by gabe.freedesktop.org (Postfix) with ESMTP id 50C766E5B3 for ; Mon, 16 Jun 2014 11:01:33 -0700 (PDT) Received: by mail-wg0-f52.google.com with SMTP id b13so6001172wgh.35 for ; Mon, 16 Jun 2014 11:01:32 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140616083239.GG27580@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Cc: Daniel Vetter , Intel Graphics Development , Aleks , stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Jun 16, 2014 at 11:32:39AM +0300, Ville Syrj=E4l=E4 wrote: > On Sun, Jun 15, 2014 at 02:55:42PM +0200, Daniel Vetter wrote: > > It changes at runtime and so should be ignored for pipe state checks. > > Note that we don't yet read out the full DRRS state, so there's some > > gaps. Bu DRRS is also not yet enabled for LVDS by default. > > = > > Cc: Aleks > > Reported-by: Aleks > > Cc: stable@vger.kernel.org > > Signed-off-by: Daniel Vetter > > --- > > drivers/gpu/drm/i915/intel_display.c | 3 +++ > > 1 file changed, 3 insertions(+) > > = > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i91= 5/intel_display.c > > index ba1d9aac3958..1ccf660e67d9 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -8549,6 +8549,9 @@ static void i9xx_crtc_clock_get(struct intel_crtc= *crtc, > > else > > fp =3D pipe_config->dpll_hw_state.fp1; > > = > > + /* We don't compute the FPA 0/1 selector. */ > > + dpll &=3D ~DISPLAY_RATE_SELECT_FPA1; > > + > = > But we still compute port_clock based on the currently active FPA > register. Won't that make the clock checks fail as well? Well yeah, but that should get solved as part of the DRRS stuff I think. Imo ignore the frequency selector for the dpll state is the right thing. DRRS with state readout is still in-flux and unsolved wrt fastbooting. Should I add a caveat to the commit message that this isn't everything or not worth it as-is? -Daniel > = > > clock.m1 =3D (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; > > if (IS_PINEVIEW(dev)) { > > clock.n =3D ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; > > -- = > > 2.0.0 > > = > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > = > -- = > Ville Syrj=E4l=E4 > Intel OTC -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch