From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [Intel-gfx] [PATCH] drm/i915: Don't take fp 0/1 selector into account for pll state Date: Mon, 16 Jun 2014 20:45:41 +0200 Message-ID: <20140616184541.GL5821@phenom.ffwll.local> References: <1402836942-31319-1-git-send-email-daniel.vetter@ffwll.ch> <20140616083239.GG27580@intel.com> <20140616180125.GD5821@phenom.ffwll.local> <20140616182035.GJ27580@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Content-Disposition: inline In-Reply-To: <20140616182035.GJ27580@intel.com> Sender: stable-owner@vger.kernel.org To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Cc: Daniel Vetter , Daniel Vetter , Intel Graphics Development , Aleks , stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Jun 16, 2014 at 09:20:35PM +0300, Ville Syrj=E4l=E4 wrote: > On Mon, Jun 16, 2014 at 08:01:26PM +0200, Daniel Vetter wrote: > > On Mon, Jun 16, 2014 at 11:32:39AM +0300, Ville Syrj=E4l=E4 wrote: > > > On Sun, Jun 15, 2014 at 02:55:42PM +0200, Daniel Vetter wrote: > > > > It changes at runtime and so should be ignored for pipe state c= hecks. > > > > Note that we don't yet read out the full DRRS state, so there's= some > > > > gaps. Bu DRRS is also not yet enabled for LVDS by default. > > > >=20 > > > > Cc: Aleks > > > > Reported-by: Aleks > > > > Cc: stable@vger.kernel.org > > > > Signed-off-by: Daniel Vetter > > > > --- > > > > drivers/gpu/drm/i915/intel_display.c | 3 +++ > > > > 1 file changed, 3 insertions(+) > > > >=20 > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu= /drm/i915/intel_display.c > > > > index ba1d9aac3958..1ccf660e67d9 100644 > > > > --- a/drivers/gpu/drm/i915/intel_display.c > > > > +++ b/drivers/gpu/drm/i915/intel_display.c > > > > @@ -8549,6 +8549,9 @@ static void i9xx_crtc_clock_get(struct in= tel_crtc *crtc, > > > > else > > > > fp =3D pipe_config->dpll_hw_state.fp1; > > > > =20 > > > > + /* We don't compute the FPA 0/1 selector. */ > > > > + dpll &=3D ~DISPLAY_RATE_SELECT_FPA1; > > > > + > > >=20 > > > But we still compute port_clock based on the currently active FPA > > > register. Won't that make the clock checks fail as well? > >=20 > > Well yeah, but that should get solved as part of the DRRS stuff I t= hink. > > Imo ignore the frequency selector for the dpll state is the right t= hing. > >=20 > > DRRS with state readout is still in-flux and unsolved wrt fastbooti= ng. > >=20 > > Should I add a caveat to the commit message that this isn't everyth= ing or > > not worth it as-is? >=20 > Well, after a better look I see that this patch does absolutely nothi= ng. > You already picked the FPA register before you cleared the select bit= =2E > So you need to clear it a bit earlier in this function, or even go as > far as clearing it when we read out the dpll state. Maybe the latter > is better in case we want to start checking the entire dpll state? Hm, I guess I hide in shame and will leave this topic to people with cl= ue ;-) Thanks for looking at this anyway. -Daniel --=20 Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch