From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH v5] drm/i915: Added write-enable pte bit
 support
Date: Tue, 17 Jun 2014 09:22:07 +0200
Message-ID: <20140617072207.GN5821@phenom.ffwll.local>
References: <1402948214.5147.9.camel@ideak-mobl>
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On Tue, Jun 17, 2014 at 10:59:42AM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> This adds support for a write-enable bit in the entry of GTT.
> This is handled via a read-only flag in the GEM buffer object which
> is then used to see how to set the bit when writing the GTT entries.
> Currently by default the Batch buffer & Ring buffers are marked as read only.
> 
> v2: Moved the pte override code for read-only bit to 'byt_pte_encode'. (Chris)
>     Fixed the issue of leaving 'gt_old_ro' as unused. (Chris)
> 
> v3: Removed the 'gt_old_ro' field, now setting RO bit only for Ring Buffers(Daniel).
> 
> v4: Added a new 'flags' parameter to all the pte(gen6) encode & insert_entries functions,
>     in lieu of overloading the cache_level enum (Daniel).
> 
> v5: Removed the superfluous VLV check & changed the definition location of PTE_READ_ONLY flag (Imre)
> 
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Akash Goel <akash.goel@intel.com>

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch