From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 14/15] drm/i915: Track frontbuffer
 invalidation/flushing
Date: Tue, 17 Jun 2014 09:52:17 +0200
Message-ID: <20140617075217.GZ5821@phenom.ffwll.local>
References: <1402941095-27879-1-git-send-email-daniel.vetter@ffwll.ch>
 <1402941095-27879-15-git-send-email-daniel.vetter@ffwll.ch>
 <20140617070005.GI17744@nuc-i3427.alporthouse.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <intel-gfx-bounces@lists.freedesktop.org>
Received: from mail-wi0-f179.google.com (mail-wi0-f179.google.com
 [209.85.212.179])
 by gabe.freedesktop.org (Postfix) with ESMTP id 929976E3A4
 for <intel-gfx@lists.freedesktop.org>; Tue, 17 Jun 2014 00:52:25 -0700 (PDT)
Received: by mail-wi0-f179.google.com with SMTP id cc10so5286890wib.12
 for <intel-gfx@lists.freedesktop.org>; Tue, 17 Jun 2014 00:52:24 -0700 (PDT)
Content-Disposition: inline
In-Reply-To: <20140617070005.GI17744@nuc-i3427.alporthouse.com>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
 <mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
 <mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Errors-To: intel-gfx-bounces@lists.freedesktop.org
Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
To: Chris Wilson <chris@chris-wilson.co.uk>, Daniel Vetter <daniel.vetter@ffwll.ch>, Intel Graphics Development <intel-gfx@lists.freedesktop.org>, Rodrigo Vivi <rodrigo.vivi@intel.com>
List-Id: intel-gfx@lists.freedesktop.org

On Tue, Jun 17, 2014 at 08:00:05AM +0100, Chris Wilson wrote:
> On Mon, Jun 16, 2014 at 07:51:34PM +0200, Daniel Vetter wrote:
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index b8359f4a6dc4..dfdbf2a02844 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -2755,6 +2755,8 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
> >  
> >  	dev_priv->display.update_primary_plane(crtc, fb, x, y);
> >  
> > +	intel_frontbuffer_flush(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
> 
> Conceptually all of these are just intel_fb_flip_complete. It may be
> easier in your tracking scheme to have:
> 
> intel_fb_flip() { intel_fb_flip_prepare(); intel_fb_fip_complete(); }

Yeah, this is just the direct flush for synchronous updates. Implementing
that as a prepare+complete is imo too confusing - the entire point of
prepare+complete is to catch an intermediate invalidates and not complete
the flush and so only really required for async flips. Hence why I prefer
to only do the full prepare+complete dance where needed. Otherwise there
is nothing special about flips.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch