From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH] drm/i915: cache hw power well enabled state
Date: Thu, 19 Jun 2014 13:45:21 +0200
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On Fri, Jun 06, 2014 at 08:37:48PM +0300, Imre Deak wrote:
> On Fri, 2014-06-06 at 19:19 +0200, Daniel Vetter wrote:
> > On Thu, Jun 05, 2014 at 08:31:47PM +0300, Imre Deak wrote:
> > > Jesse noticed that the punit communication needed to query the VLV power
> > > well status can cause substantial delays. Since we can query the state
> > > frequently, for example during I2C transfers, maintain a cached version
> > > of the HW state to get rid of this delay.
> > > 
> > > This fixes at least one reported regression where boot time increased by
> > > ~4 seconds due to frequent power well state queries on VLV during eDP
> > > EDID read.
> > > 
> > > Reported-by: Jesse Barnes <jesse.barnes@intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > 
> > A citation for the regressing commit here (i.e. the one that enabled vlv
> > runtime pm) would be good so that Jani can pick it up.
> 
> I'm not aware of any other case where we had a significant overhead, so
> for the above particular issue I'd say
> 
> this was introduced by
> 
> commit bb4932c4f17b68f34645ffbcf845e4c29d17290b
> Author: Imre Deak <imre.deak@intel.com>
> Date:   Mon Apr 14 20:24:33 2014 +0300
> 
>     drm/i915: vlv: check port power domain instead of only D0 for eDP
> VDD on

Ok since Jani's out I've merged this.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch