From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 2/2] drm/i915: don't take runtime PM reference around freeze/thaw Date: Thu, 19 Jun 2014 18:05:46 +0200 Message-ID: <20140619160546.GW5821@phenom.ffwll.local> References: <1403110376-1889-1-git-send-email-jbarnes@virtuousgeek.org> <1403110376-1889-2-git-send-email-jbarnes@virtuousgeek.org> <1403184355.27481.8.camel@intelbox> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wi0-f175.google.com (mail-wi0-f175.google.com [209.85.212.175]) by gabe.freedesktop.org (Postfix) with ESMTP id C97E96E8D5 for ; Thu, 19 Jun 2014 09:05:55 -0700 (PDT) Received: by mail-wi0-f175.google.com with SMTP id r20so9639467wiv.2 for ; Thu, 19 Jun 2014 09:05:55 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1403184355.27481.8.camel@intelbox> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Imre Deak Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Jun 19, 2014 at 04:25:55PM +0300, Imre Deak wrote: > On Wed, 2014-06-18 at 09:52 -0700, Jesse Barnes wrote: > > We should be taking the right power well refs these days, so this > > shouldn't be necessary. It also gets in the way of re-using these > > routines for S0iX states, as those need all the power saving features > > enabled. > > > > Signed-off-by: Jesse Barnes > > Reviewed-by: Imre Deak > > Btw, we also have the same redundancy in intel_dp_detect(). Both patches merged, thanks. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch