From mboxrd@z Thu Jan 1 00:00:00 1970 From: Damien Lespiau Subject: Re: [PATCH 2/3] drm/i915: Add 180 degree primary plane rotation support Date: Tue, 24 Jun 2014 11:29:30 +0100 Message-ID: <20140624102930.GD11357@strange.amr.corp.intel.com> References: <20140619082148.GR5821@phenom.ffwll.local> <1403501761-15049-1-git-send-email-sonika.jindal@intel.com> <1403501761-15049-3-git-send-email-sonika.jindal@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 8D2A96E4F2 for ; Tue, 24 Jun 2014 03:29:32 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1403501761-15049-3-git-send-email-sonika.jindal@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: sonika.jindal@intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Jun 23, 2014 at 11:06:00AM +0530, sonika.jindal@intel.com wrote: > From: Sonika Jindal > = > Primary planes support 180 degree rotation. Expose the feature > through rotation drm property. > = > v2: Calculating linear/tiled offsets based on pipe source width and > height. Added 180 degree rotation support in ironlake_update_plane. > = > v3: Checking if CRTC is active before issueing update_plane. Added > wait for vblank to make sure we dont overtake page flips. Disabling > FBC since it does not work with rotated planes. > = > v4: Updated rotation checks for pending flips, fbc disable. Creating > rotation property only for Gen4 onwards. Property resetting as part > of lastclose. > = > v5: Resetting property in i915_driver_lastclose properly for planes > and crtcs. Fixed linear offset calculation that was off by 1 w.r.t > width in i9xx_update_plane and ironlake_update_plane. Removed tab > based indentation and unnecessary braces in intel_crtc_set_property > and intel_update_fbc. FBC and flip related checks should be done only > for valid crtcs. > = > v6: Minor nits in FBC disable checks for comments in intel_crtc_set_prope= rty > and positioning the disable code in intel_update_fbc. > = > v7: In case rotation property on inactive crtc is updated, we return > successfully printing debug log as crtc is inactive and only property cha= nge > is preserved. > = > v8: update_plane is changed to update_primary_plane, crtc->fb is changed = to > crtc->primary->fb and return value of update_primary_plane is ignored. > = > v9: added rotation property to primary plane instead of crtc. Removing re= set > of rotation property from lastclose. rotation_property is moved to drm_pl= ane,so > drm layer will take care of resetting. > = > Testcase: igt/kms_rotation_crc > = > Cc: Daniel Vetter > Cc: Jani Nikula > Cc: dri-devel@lists.freedesktop.org > Cc: vijay.a.purushothaman@intel.com > Signed-off-by: Uma Shankar > Signed-off-by: Sagar Kamble > Reviewed-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/i915_dma.c | 5 -- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_display.c | 94 ++++++++++++++++++++++++++++= ++++-- > drivers/gpu/drm/i915/intel_pm.c | 8 +++ > 4 files changed, 98 insertions(+), 10 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_= dma.c > index 5e583a1..4b6b911 100644 > --- a/drivers/gpu/drm/i915/i915_dma.c > +++ b/drivers/gpu/drm/i915/i915_dma.c > @@ -1938,14 +1938,9 @@ int i915_driver_open(struct drm_device *dev, struc= t drm_file *file) > */ > void i915_driver_lastclose(struct drm_device *dev) > { > - struct drm_i915_private *dev_priv =3D dev->dev_private; > - > /* On gen6+ we refuse to init without kms enabled, but then the drm core > * goes right around and calls lastclose. Check for this and don't clean > * up anything. */ > - if (!dev_priv) > - return; > - > if (drm_core_check_feature(dev, DRIVER_MODESET)) { > intel_fbdev_restore_mode(dev); > vga_switcheroo_process_delayed_switch(); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index c70c804..c600d3b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4087,6 +4087,7 @@ enum punit_power_well { > #define DISPPLANE_NO_LINE_DOUBLE 0 > #define DISPPLANE_STEREO_POLARITY_FIRST 0 > #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) > +#define DISPPLANE_ROTATE_180 (1<<15) > #define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ > #define DISPPLANE_TILED (1<<10) > #define _DSPAADDR 0x70184 > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index 5e8e711..85bd3b8 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2414,7 +2414,9 @@ static void i9xx_update_primary_plane(struct drm_cr= tc *crtc, > unsigned long linear_offset; > u32 dspcntr; > u32 reg; > + int pixel_size; > = > + pixel_size =3D drm_format_plane_cpp(fb->pixel_format, 0); > intel_fb =3D to_intel_framebuffer(fb); > obj =3D intel_fb->obj; > = > @@ -2422,6 +2424,8 @@ static void i9xx_update_primary_plane(struct drm_cr= tc *crtc, > dspcntr =3D I915_READ(reg); > /* Mask out pixel format bits in case we change it */ > dspcntr &=3D ~DISPPLANE_PIXFORMAT_MASK; > + dspcntr &=3D ~DISPPLANE_ROTATE_180; > + > switch (fb->pixel_format) { > case DRM_FORMAT_C8: > dspcntr |=3D DISPPLANE_8BPP; > @@ -2463,8 +2467,6 @@ static void i9xx_update_primary_plane(struct drm_cr= tc *crtc, > if (IS_G4X(dev)) > dspcntr |=3D DISPPLANE_TRICKLE_FEED_DISABLE; > = > - I915_WRITE(reg, dspcntr); > - > linear_offset =3D y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); > = > if (INTEL_INFO(dev)->gen >=3D 4) { > @@ -2477,6 +2479,17 @@ static void i9xx_update_primary_plane(struct drm_c= rtc *crtc, > intel_crtc->dspaddr_offset =3D linear_offset; > } > = > + if (to_intel_plane(crtc->primary)->rotation =3D=3D BIT(DRM_ROTATE_180))= { > + dspcntr |=3D DISPPLANE_ROTATE_180; > + > + x +=3D (intel_crtc->config.pipe_src_w - 1); > + y +=3D (intel_crtc->config.pipe_src_h - 1); > + linear_offset +=3D (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0= ] + > + (intel_crtc->config.pipe_src_w - 1) * pixel_size; > + } > + > + I915_WRITE(reg, dspcntr); > + > DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", > i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, > fb->pitches[0]); > @@ -2487,7 +2500,8 @@ static void i9xx_update_primary_plane(struct drm_cr= tc *crtc, > I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); > I915_WRITE(DSPLINOFF(plane), linear_offset); > } else > - I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offs= et); > + I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + > + linear_offset); > POSTING_READ(reg); > } > = > @@ -2504,7 +2518,9 @@ static void ironlake_update_primary_plane(struct dr= m_crtc *crtc, > unsigned long linear_offset; > u32 dspcntr; > u32 reg; > + int pixel_size; > = > + pixel_size =3D drm_format_plane_cpp(fb->pixel_format, 0); > intel_fb =3D to_intel_framebuffer(fb); > obj =3D intel_fb->obj; > = > @@ -2512,6 +2528,8 @@ static void ironlake_update_primary_plane(struct dr= m_crtc *crtc, > dspcntr =3D I915_READ(reg); > /* Mask out pixel format bits in case we change it */ > dspcntr &=3D ~DISPPLANE_PIXFORMAT_MASK; > + dspcntr &=3D ~DISPPLANE_ROTATE_180; > + > switch (fb->pixel_format) { > case DRM_FORMAT_C8: > dspcntr |=3D DISPPLANE_8BPP; > @@ -2549,8 +2567,6 @@ static void ironlake_update_primary_plane(struct dr= m_crtc *crtc, > else > dspcntr |=3D DISPPLANE_TRICKLE_FEED_DISABLE; > = > - I915_WRITE(reg, dspcntr); > - > linear_offset =3D y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); > intel_crtc->dspaddr_offset =3D > intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, > @@ -2558,6 +2574,20 @@ static void ironlake_update_primary_plane(struct d= rm_crtc *crtc, > fb->pitches[0]); > linear_offset -=3D intel_crtc->dspaddr_offset; > = > + if (to_intel_plane(crtc->primary)->rotation =3D=3D BIT(DRM_ROTATE_180))= { > + dspcntr |=3D DISPPLANE_ROTATE_180; > + > + if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { > + x +=3D (intel_crtc->config.pipe_src_w - 1); > + y +=3D (intel_crtc->config.pipe_src_h - 1); > + linear_offset +=3D (intel_crtc->config.pipe_src_h - 1) * > + fb->pitches[0] + (intel_crtc->config.pipe_src_w - 1) * > + pixel_size; > + } > + } > + > + I915_WRITE(reg, dspcntr); > + > DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", > i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, > fb->pitches[0]); > @@ -11324,10 +11354,50 @@ static void intel_plane_destroy(struct drm_plan= e *plane) > kfree(intel_plane); > } > = > +static int intel_primary_plane_set_property(struct drm_plane *plane, > + struct drm_property *prop, > + uint64_t val) > +{ > + struct drm_device *dev =3D plane->dev; > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + struct intel_plane *intel_plane =3D to_intel_plane(plane); > + struct intel_crtc *intel_crtc =3D to_intel_crtc(plane->crtc); > + struct drm_crtc *crtc =3D &intel_crtc->base; > + uint64_t old_val; > + > + if (prop =3D=3D plane->rotation_property) { > + /* exactly one rotation angle please */ > + if (hweight32(val & 0xf) !=3D 1) > + return -EINVAL; > + > + old_val =3D intel_plane->rotation; > + intel_plane->rotation =3D val; > + > + if (intel_crtc->active && intel_crtc->primary_enabled) { > + intel_crtc_wait_for_pending_flips(crtc); > + > + /* FBC does not work on some platforms for rotated planes */ > + if (dev_priv->fbc.plane =3D=3D intel_crtc->plane && > + INTEL_INFO(dev)->gen <=3D 4 && !IS_G4X(dev) && > + intel_plane->rotation !=3D BIT(DRM_ROTATE_0)) > + intel_disable_fbc(dev); > + dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, > + 0, 0); > + > + } else { > + DRM_DEBUG_KMS("[CRTC:%d] is not active. Only rotation property is upd= ated\n", > + crtc->base.id); > + } > + } > + > + return 0; > +} > + > static const struct drm_plane_funcs intel_primary_plane_funcs =3D { > .update_plane =3D intel_primary_plane_setplane, > .disable_plane =3D intel_primary_plane_disable, > .destroy =3D intel_plane_destroy, > + .set_property =3D intel_primary_plane_set_property > }; > = > static struct drm_plane *intel_primary_plane_create(struct drm_device *d= ev, > @@ -11335,6 +11405,7 @@ static struct drm_plane *intel_primary_plane_crea= te(struct drm_device *dev, > { > struct intel_plane *primary; > const uint32_t *intel_primary_formats; > + struct drm_i915_private *dev_priv =3D dev->dev_private; > int num_formats; Here and elsewhere, you're adding dev_priv to remove it in the next patch. A left over from putting the rotation property in drm_plane. -- = Damien