From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915: vlv_prepare_pll is only needed in case of non DSI interfaces Date: Tue, 24 Jun 2014 16:45:50 +0300 Message-ID: <20140624134550.GX27580@intel.com> References: <1403616099-12007-1-git-send-email-shobhit.kumar@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 3AD236E51D for ; Tue, 24 Jun 2014 06:45:54 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1403616099-12007-1-git-send-email-shobhit.kumar@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Shobhit Kumar Cc: Jani Nikula , Daniel Vetter , intel-gfx List-Id: intel-gfx@lists.freedesktop.org On Tue, Jun 24, 2014 at 06:51:39PM +0530, Shobhit Kumar wrote: > For MIPI, DSI PLL is configured separately in vlv_configure_dsi_pll > during the DSI enable sequence > = > Causing WARN dump otherwise in dpio_reads > = > Signed-off-by: Shobhit Kumar Yeah, the DPIO power wells might be down when enabling a DSI display so we shouldn't go poking at DPIO registers. But please add a !IS_CHERRYVIEW check there also, and then you can add: Reviewed-by: Ville Syrj=E4l=E4 Looks like I need to split up chv_update_pll() in a similar fasion. > --- > drivers/gpu/drm/i915/intel_display.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index fa77557..2fa7152 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4629,7 +4629,10 @@ static void valleyview_crtc_enable(struct drm_crtc= *crtc) > if (intel_crtc->active) > return; > = > - vlv_prepare_pll(intel_crtc); > + is_dsi =3D intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); > + > + if (!is_dsi) > + vlv_prepare_pll(intel_crtc); > = > /* Set up the display plane register */ > dspcntr =3D DISPPLANE_GAMMA_ENABLE; > @@ -4663,8 +4666,6 @@ static void valleyview_crtc_enable(struct drm_crtc = *crtc) > if (encoder->pre_pll_enable) > encoder->pre_pll_enable(encoder); > = > - is_dsi =3D intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); > - > if (!is_dsi) { > if (IS_CHERRYVIEW(dev)) > chv_enable_pll(intel_crtc); > -- = > 1.9.1 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC