Re: [PATCH 01/11] drm/i915: Change vlv cdclk to use kHz units

[Jesse Barnes <jbarnes@virtuousgeek.org>]

On Fri, 13 Jun 2014 13:37:47 +0300
ville.syrjala@linux.intel.com wrote:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Use kHz units in vlv cdclk code since that's more customary.
> 
> Also replace the precomputed 90% values with *9/10 computation
> for extra clarity.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++-------------
>  drivers/gpu/drm/i915/intel_i2c.c     |  2 +-
>  drivers/gpu/drm/i915/intel_pm.c      |  2 +-
>  3 files changed, 16 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5762726..5f66dc8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4429,6 +4429,7 @@ static void modeset_update_crtc_power_domains(struct drm_device *dev)
>  	intel_display_set_init_power(dev_priv, false);
>  }
>  
> +/* returns HPLL frequency in kHz */
>  int valleyview_get_vco(struct drm_i915_private *dev_priv)
>  {
>  	int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
> @@ -4439,7 +4440,7 @@ int valleyview_get_vco(struct drm_i915_private *dev_priv)
>  		CCK_FUSE_HPLL_FREQ_MASK;
>  	mutex_unlock(&dev_priv->dpio_lock);
>  
> -	return vco_freq[hpll_freq];
> +	return vco_freq[hpll_freq] * 1000;
>  }
>  
>  /* Adjust CDclk dividers to allow high res or save power if possible */
> @@ -4451,9 +4452,9 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
>  	WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
>  	dev_priv->vlv_cdclk_freq = cdclk;
>  
> -	if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
> +	if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
>  		cmd = 2;
> -	else if (cdclk == 266)
> +	else if (cdclk == 266667)
>  		cmd = 1;
>  	else
>  		cmd = 0;
> @@ -4470,11 +4471,11 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
>  	}
>  	mutex_unlock(&dev_priv->rps.hw_lock);
>  
> -	if (cdclk == 400) {
> +	if (cdclk == 400000) {
>  		u32 divider, vco;
>  
>  		vco = valleyview_get_vco(dev_priv);
> -		divider = ((vco << 1) / cdclk) - 1;
> +		divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
>  
>  		mutex_lock(&dev_priv->dpio_lock);
>  		/* adjust cdclk divider */
> @@ -4494,7 +4495,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
>  	 * For high bandwidth configs, we set a higher latency in the bunit
>  	 * so that the core display fetch happens in time to avoid underruns.
>  	 */
> -	if (cdclk == 400)
> +	if (cdclk == 400000)
>  		val |= 4500 / 250; /* 4.5 usec */
>  	else
>  		val |= 3000 / 250; /* 3.0 usec */
> @@ -4518,7 +4519,7 @@ int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
>  
>  	divider &= 0xf;
>  
> -	cur_cdclk = (vco << 1) / (divider + 1);
> +	cur_cdclk = DIV_ROUND_CLOSEST(vco << 1, divider + 1);
>  
>  	return cur_cdclk;
>  }
> @@ -4535,12 +4536,12 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
>  	 * So we check to see whether we're above 90% of the lower bin and
>  	 * adjust if needed.
>  	 */
> -	if (max_pixclk > 288000) {
> -		return 400;
> -	} else if (max_pixclk > 240000) {
> -		return 320;
> -	} else
> -		return 266;
> +	if (max_pixclk > 320000*9/10)
> +		return 400000;
> +	else if (max_pixclk > 266667*9/10)
> +		return 320000;
> +	else
> +		return 266667;
>  	/* Looks like the 200MHz CDclk freq doesn't work on some configs */
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index d33b61d..9ce4f09 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -86,7 +86,7 @@ static void gmbus_set_freq(struct drm_i915_private *dev_priv)
>  
>  	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
>  
> -	vco = valleyview_get_vco(dev_priv);
> +	vco = valleyview_get_vco(dev_priv) / 1000;
>  
>  	/* Get the CDCLK divide ratio */
>  	cdclk_div = get_disp_clk_div(dev_priv, CDCLK);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5024bc8..a9ddf74 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5536,7 +5536,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
>  
>  	dev_priv->vlv_cdclk_freq = valleyview_cur_cdclk(dev_priv);
> -	DRM_DEBUG_DRIVER("Current CD clock rate: %d MHz",
> +	DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
>  			 dev_priv->vlv_cdclk_freq);
>  
>  	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center
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