From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 05/11] drm/i915: Use 200MHz cdclk on vlv when all pipes are off
Date: Wed, 25 Jun 2014 22:32:17 +0300 [thread overview]
Message-ID: <20140625193217.GA27580@intel.com> (raw)
In-Reply-To: <20140625115406.0a98fcfa@jbarnes-desktop>
On Wed, Jun 25, 2014 at 11:54:06AM -0700, Jesse Barnes wrote:
> On Fri, 13 Jun 2014 13:37:51 +0300
> ville.syrjala@linux.intel.com wrote:
>
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Drop the cdclk frequency to 200MHz on vlv when all pipes are off. In
> > theory we should be able to use 200MHz also when the pixel clock is at
> > most 90% of 200MHz. However in practice all we seem to get is a solid
> > color picture or an otherwise corrupted display.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 9 +++++++--
> > 1 file changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 1f3985f..3a9b017 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4520,14 +4520,19 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
> > * 400MHz
> > * So we check to see whether we're above 90% of the lower bin and
> > * adjust if needed.
> > + *
> > + * We seem to get an unstable or solid color picture at 200MHz.
> > + * Not sure what's wrong. For now use 200MHz only when all pipes
> > + * are off.
> > */
> > if (max_pixclk > freq_320*9/10)
> > return 400000;
> > else if (max_pixclk > 266667*9/10)
> > return freq_320;
> > - else
> > + else if (max_pixclk > 0)
> > return 266667;
> > - /* Looks like the 200MHz CDclk freq doesn't work on some configs */
> > + else
> > + return 200000;
> > }
> >
> > /* compute the max pixel clock for new configuration */
>
> I guess this is safe, but optional (won't we be shutting off the clocks
> anyway?).
Ideally yes. But currently I'm not sure if that happens.
>
> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>
> --
> Jesse Barnes, Intel Open Source Technology Center
--
Ville Syrjälä
Intel OTC
next prev parent reply other threads:[~2014-06-25 19:32 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-13 10:37 [PATCH 00/11] drm/i915: VLV display clock/phy stuff ville.syrjala
2014-06-13 10:37 ` [PATCH 01/11] drm/i915: Change vlv cdclk to use kHz units ville.syrjala
2014-06-25 18:36 ` Jesse Barnes
2014-06-13 10:37 ` [PATCH 02/11] drm/i915: Give names to the CCK_DISPLAY_CLOCK_CONTROL bits ville.syrjala
2014-06-25 18:45 ` Jesse Barnes
2014-06-13 10:37 ` [PATCH 03/11] drm/i915: Move vlv cdclk code to .get_display_clock_speed() ville.syrjala
2014-06-25 18:47 ` Jesse Barnes
2014-07-07 9:17 ` Daniel Vetter
2014-06-13 10:37 ` [PATCH 04/11] drm/i915: Handle 320 vs. 333 MHz cdclk on vlv ville.syrjala
2014-06-25 18:53 ` Jesse Barnes
2014-06-13 10:37 ` [PATCH 05/11] drm/i915: Use 200MHz cdclk on vlv when all pipes are off ville.syrjala
2014-06-25 18:54 ` Jesse Barnes
2014-06-25 19:32 ` Ville Syrjälä [this message]
2014-06-13 10:37 ` [PATCH 06/11] drm/i915: Wait for cdclk change to occure when going for 400MHz ville.syrjala
2014-06-25 18:54 ` Jesse Barnes
2014-06-13 10:37 ` [PATCH 07/11] drm/i915: Warn if there's a cdclk change in progess ville.syrjala
2014-06-25 18:55 ` Jesse Barnes
2014-06-25 19:34 ` Ville Syrjälä
2014-07-07 9:26 ` Daniel Vetter
2014-06-13 10:37 ` [PATCH 08/11] drm/i915: Kill duplicated cdclk readout code from i2c ville.syrjala
2014-06-25 18:58 ` Jesse Barnes
2014-06-13 10:37 ` [PATCH 09/11] drm/i915: Pull the cmnlane tricks into its own power well ops ville.syrjala
2014-06-25 18:59 ` Jesse Barnes
2014-06-13 10:37 ` [PATCH 10/11] drm/i915: Move VLV cmnlane workaround to intel_power_domains_init_hw() ville.syrjala
2014-06-25 19:03 ` Jesse Barnes
2014-06-25 19:43 ` Ville Syrjälä
2014-06-13 10:37 ` [WIP][PATCH 11/11] drm/i915: Turn off clocks when disp2d is powered down ville.syrjala
2014-06-25 19:03 ` Jesse Barnes
2014-07-07 9:30 ` Daniel Vetter
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