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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 07/11] drm/i915: Warn if there's a cdclk change in progess
Date: Wed, 25 Jun 2014 22:34:48 +0300	[thread overview]
Message-ID: <20140625193448.GB27580@intel.com> (raw)
In-Reply-To: <20140625115558.645bb288@jbarnes-desktop>

On Wed, Jun 25, 2014 at 11:55:58AM -0700, Jesse Barnes wrote:
> On Fri, 13 Jun 2014 13:37:53 +0300
> ville.syrjala@linux.intel.com wrote:
> 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > If someone is interested in the current cdclk frquency it should
> > be stable and not in process of changing frquency. Warn if the current
> > and requested cdclk don't match in .get_display_clock_spee() on vlv.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 29dddec..601e97e 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5234,6 +5234,10 @@ static int valleyview_get_display_clock_speed(struct drm_device *dev)
> >  
> >  	divider = val & DISPLAY_FREQUENCY_VALUES;
> >  
> > +	WARN((val & DISPLAY_FREQUENCY_STATUS) !=
> > +	     (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
> > +	     "cdclk change in progress\n");
> > +
> >  	return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
> >  }
> >  
> 
> Hm, there's not much we can do in this case, so rather than warn maybe
> we should try a wait instead, and only warn if it times out?  Even then
> there's not much we can do aside from poking the PUnit folks.

This shouldn't happen unless we somehow messed up and triggered a cdclk
change and didn't wait for it to complete, which would be a driver bug.
So I think a simple WARN seems sufficient.

-- 
Ville Syrjälä
Intel OTC

  reply	other threads:[~2014-06-25 19:35 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-13 10:37 [PATCH 00/11] drm/i915: VLV display clock/phy stuff ville.syrjala
2014-06-13 10:37 ` [PATCH 01/11] drm/i915: Change vlv cdclk to use kHz units ville.syrjala
2014-06-25 18:36   ` Jesse Barnes
2014-06-13 10:37 ` [PATCH 02/11] drm/i915: Give names to the CCK_DISPLAY_CLOCK_CONTROL bits ville.syrjala
2014-06-25 18:45   ` Jesse Barnes
2014-06-13 10:37 ` [PATCH 03/11] drm/i915: Move vlv cdclk code to .get_display_clock_speed() ville.syrjala
2014-06-25 18:47   ` Jesse Barnes
2014-07-07  9:17     ` Daniel Vetter
2014-06-13 10:37 ` [PATCH 04/11] drm/i915: Handle 320 vs. 333 MHz cdclk on vlv ville.syrjala
2014-06-25 18:53   ` Jesse Barnes
2014-06-13 10:37 ` [PATCH 05/11] drm/i915: Use 200MHz cdclk on vlv when all pipes are off ville.syrjala
2014-06-25 18:54   ` Jesse Barnes
2014-06-25 19:32     ` Ville Syrjälä
2014-06-13 10:37 ` [PATCH 06/11] drm/i915: Wait for cdclk change to occure when going for 400MHz ville.syrjala
2014-06-25 18:54   ` Jesse Barnes
2014-06-13 10:37 ` [PATCH 07/11] drm/i915: Warn if there's a cdclk change in progess ville.syrjala
2014-06-25 18:55   ` Jesse Barnes
2014-06-25 19:34     ` Ville Syrjälä [this message]
2014-07-07  9:26       ` Daniel Vetter
2014-06-13 10:37 ` [PATCH 08/11] drm/i915: Kill duplicated cdclk readout code from i2c ville.syrjala
2014-06-25 18:58   ` Jesse Barnes
2014-06-13 10:37 ` [PATCH 09/11] drm/i915: Pull the cmnlane tricks into its own power well ops ville.syrjala
2014-06-25 18:59   ` Jesse Barnes
2014-06-13 10:37 ` [PATCH 10/11] drm/i915: Move VLV cmnlane workaround to intel_power_domains_init_hw() ville.syrjala
2014-06-25 19:03   ` Jesse Barnes
2014-06-25 19:43     ` Ville Syrjälä
2014-06-13 10:37 ` [WIP][PATCH 11/11] drm/i915: Turn off clocks when disp2d is powered down ville.syrjala
2014-06-25 19:03   ` Jesse Barnes
2014-07-07  9:30     ` Daniel Vetter

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