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From: Daniel Vetter <daniel@ffwll.ch>
To: "Chen, Tiejun" <tiejun.chen@intel.com>
Cc: xen-devel@lists.xensource.com, dri-devel@lists.freedesktop.org,
	daniel.vetter@ffwll.ch, intel-gfx@lists.freedesktop.org,
	linux-kernel@vger.kernel.org, qemu-devel@nongnu.org
Subject: Re: [Intel-gfx] [RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type
Date: Mon, 7 Jul 2014 16:51:20 +0200	[thread overview]
Message-ID: <20140707145120.GA5821@phenom.ffwll.local> (raw)
In-Reply-To: <53AA33C5.7060501@intel.com>

On Wed, Jun 25, 2014 at 10:28:21AM +0800, Chen, Tiejun wrote:
> On 2014/6/24 10:59, Zhenyu Wang wrote:
> >On 2014.06.19 17:53:51 +0800, Tiejun Chen wrote:
> >>Originally the reason to probe ISA bridge instead of Dev31:Fun0
> >>is to make graphics device passthrough work easy for VMM, that
> >>only need to expose ISA bridge to let driver know the real
> >>hardware underneath. This is a requirement from virtualization
> >>team. Especially in that virtualized environments, XEN, there
> >>is irrelevant ISA bridge in the system with that legacy qemu
> >>version specific to xen, qemu-xen-traditional. So to work
> >>reliably, we should scan through all the ISA bridge devices
> >>and check for the first match, instead of only checking the
> >>first one.
> >>
> >>But actually, qemu-xen-traditional, is always enumerated with
> >>Dev31:Fun0, 00:1f.0 as follows:
> >>
> >>hw/pt-graphics.c:
> >>
> >>intel_pch_init()
> >>     |
> >>     + pci_isa_bridge_init(bus, PCI_DEVFN(0x1f, 0), ...);
> >>
> >>so this mean that isa bridge is still represented with Dev31:Func0
> >>like the native OS. Furthermore, currently we're pushing VGA
> >>passthrough support into qemu upstream, and with some discussion,
> >>we wouldn't set the bridge class type and just expose this devfn.
> >>
> >>So we just go back to check devfn to make life normal.
> >>
> >>Signed-off-by: Tiejun Chen <tiejun.chen@intel.com>
> >
> >This was added historically when supporting graphics device passthrough.
> >Looks qemu upstream can't accept multiple ISA bridge and our PCH is always
> >on device 31: func0 as far as I know. Looks good to me.
> >
> >Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
> >
> 
> Thanks for your review.
> 
> Do you know when this can be applied?

I'll hold off merging until we have buy-in from upstream quemu on a given
approach (which should work for both linux and windows).
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

  reply	other threads:[~2014-07-07 14:51 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-19  9:53 [RFC][PATCH] gpu:drm:i915:intel_detect_pch: back to check devfn instead of check class type Tiejun Chen
2014-06-20  9:40 ` Chen, Tiejun
2014-06-20 12:32   ` Daniel Vetter
2014-06-22  8:00     ` Chen, Tiejun
2014-06-20 12:48 ` Paolo Bonzini
2014-06-22  8:25   ` Chen, Tiejun
2014-06-25  6:48     ` Paolo Bonzini
2014-06-25  7:34       ` Chen, Tiejun
2014-06-25  7:55         ` Paolo Bonzini
2014-06-30  3:13           ` Chen, Tiejun
2014-06-30 10:56             ` Paolo Bonzini
2014-07-07 14:49       ` Daniel Vetter
2014-07-07 14:57         ` Paolo Bonzini
2014-07-07 17:54           ` [Intel-gfx] " Daniel Vetter
2014-07-07 17:58             ` Paolo Bonzini
2014-07-07 18:40               ` Daniel Vetter
2014-07-10 21:08                 ` Tian, Kevin
2014-07-11  6:29                   ` [Intel-gfx] " Daniel Vetter
2014-07-11 19:42                     ` [Xen-devel] " Konrad Rzeszutek Wilk
2014-07-11 20:30                       ` Tian, Kevin
2014-07-12 10:13                         ` Daniel Vetter
2014-06-24  2:59 ` Zhenyu Wang
2014-06-25  2:28   ` Chen, Tiejun
2014-07-07 14:51     ` Daniel Vetter [this message]
2014-06-30 11:18 ` Michael S. Tsirkin
2014-07-01  1:52   ` Chen, Tiejun
2014-07-02  6:21 ` Michael S. Tsirkin
2014-07-02  8:27   ` Chen, Tiejun

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