Re: [PATCH] drm/i915: Introduce FBC False Color for debug purposes.

[Daniel Vetter <daniel@ffwll.ch>]

On Fri, Jun 20, 2014 at 06:46:06AM -0700, Rodrigo Vivi wrote:
> With this bit enabled, HW changes the color when compressing frames for
> debug purposes.
> 
> ALthough the simple way to enable a single bit is over intel_reg_write,
> this value is overwriten on next update_fbc so depending on the workload
> it is not possible to set this bit with intel-gpu-tools. So this patch
> introduces a persistent way to enable false color over debugfs.
> 
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

DEFINE_SIMPLE_ATTRIBUTE allows you do ditch a lot of boilerplate here.
Otherwise looks good and useful, please resubmit with that change and
volunteer someone for review.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 70 +++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_drv.h     |  2 ++
>  drivers/gpu/drm/i915/i915_reg.h     |  1 +
>  drivers/gpu/drm/i915/intel_pm.c     |  6 ++++
>  4 files changed, 79 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 6b7b32b..c2019a6 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1508,6 +1508,75 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
>  	return 0;
>  }
>  
> +static int i915_fbc_fc_show(struct seq_file *m, void *data)
> +{
> +	struct drm_device *dev = m->private;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	drm_modeset_lock_all(dev);
> +	seq_printf(m, "False Color: %s\n", yesno(dev_priv->fbc.false_color));
> +	drm_modeset_unlock_all(dev);
> +
> +	return 0;
> +}
> +
> +static int i915_fbc_fc_open(struct inode *inode, struct file *file)
> +{
> +	struct drm_device *dev = inode->i_private;
> +
> +	if (INTEL_INFO(dev)->gen < 5)
> +		return -ENODEV;
> +
> +	return single_open(file, i915_fbc_fc_show, dev);
> +}
> +
> +static ssize_t i915_fbc_fc_write(struct file *file, const char __user *ubuf,
> +			      size_t len, loff_t *offp)
> +{
> +	struct seq_file *m = file->private_data;
> +	struct drm_device *dev = m->private;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int ret;
> +	char tmp[2];
> +	int false_color;
> +	u32 val;
> +
> +	if (len > 2)
> +		return -EINVAL;
> +
> +	if (copy_from_user(tmp, ubuf, len))
> +		return -EFAULT;
> +
> +	tmp[1] = '\0';
> +
> +	ret = sscanf(tmp, "%d", &false_color);
> +	if (ret != 1)
> +		return -EINVAL;
> +
> +	drm_modeset_lock_all(dev);
> +
> +	val = I915_READ(ILK_DPFC_CONTROL);
> +	dev_priv->fbc.false_color = false_color;
> +
> +	I915_WRITE(ILK_DPFC_CONTROL, false_color ?
> +		   (val | FBC_CTL_FALSE_COLOR) :
> +		   (val & ~FBC_CTL_FALSE_COLOR));
> +
> +	drm_modeset_unlock_all(dev);
> +
> +	return len;
> +}
> +
> +static const struct file_operations i915_fbc_fops = {
> +	.release = single_release,
> +	.owner = THIS_MODULE,
> +	.read = seq_read,
> +	.open = i915_fbc_fc_open,
> +	.llseek = seq_lseek,
> +	.release = single_release,
> +	.write = i915_fbc_fc_write,
> +};
> +
>  static int i915_ips_status(struct seq_file *m, void *unused)
>  {
>  	struct drm_info_node *node = m->private;
> @@ -3858,6 +3927,7 @@ static const struct i915_debugfs_files {
>  	{"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
>  	{"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
>  	{"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
> +	{"i915_fbc_false_color", &i915_fbc_fops},
>  };
>  
>  void intel_display_crc_init(struct drm_device *dev)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8cea596..ec24b15 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -607,6 +607,8 @@ struct i915_fbc {
>  	struct drm_mm_node *compressed_fb;
>  	struct drm_mm_node *compressed_llb;
>  
> +	bool false_color;
> +
>  	struct intel_fbc_work {
>  		struct delayed_work work;
>  		struct drm_crtc *crtc;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3488567..c70df22 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1495,6 +1495,7 @@ enum punit_power_well {
>  /* Framebuffer compression for Ironlake */
>  #define ILK_DPFC_CB_BASE	0x43200
>  #define ILK_DPFC_CONTROL	0x43208
> +#define   FBC_CTL_FALSE_COLOR	(1<<10)
>  /* The bit 28-8 is reserved */
>  #define   DPFC_RESERVED		(0x1FFFFF00)
>  #define ILK_DPFC_RECOMP_CTL	0x4320c
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d771e82..216cb19 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -236,6 +236,9 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc)
>  	if (IS_GEN5(dev))
>  		dpfc_ctl |= obj->fence_reg;
>  
> +	if (dev_priv->fbc.false_color)
> +		dpfc_ctl |= FBC_CTL_FALSE_COLOR;
> +
>  	I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
>  	I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
>  	/* enable it... */
> @@ -290,6 +293,9 @@ static void gen7_enable_fbc(struct drm_crtc *crtc)
>  		dpfc_ctl |= DPFC_CTL_LIMIT_1X;
>  	dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
>  
> +	if (dev_priv->fbc.false_color)
> +		dpfc_ctl |= FBC_CTL_FALSE_COLOR;
> +
>  	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
>  
>  	if (IS_IVYBRIDGE(dev)) {
> -- 
> 1.9.0
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch