From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: pin OABUFFER to GGTT Date: Mon, 7 Jul 2014 22:43:33 +0200 Message-ID: <20140707204333.GC17271@phenom.ffwll.local> References: <92648605EABDA246B775AAB04C95A7A3137EB4F3@IRSMSX103.ger.corp.intel.com> <20140701163017.GA7371@nuc-i3427.alporthouse.com> <92648605EABDA246B775AAB04C95A7A3137EB523@IRSMSX103.ger.corp.intel.com> <20140701165149.GB7371@nuc-i3427.alporthouse.com> <92648605EABDA246B775AAB04C95A7A3137EB5E3@IRSMSX103.ger.corp.intel.com> <20140701195427.GA11155@nuc-i3427.alporthouse.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wg0-f50.google.com (mail-wg0-f50.google.com [74.125.82.50]) by gabe.freedesktop.org (Postfix) with ESMTP id 858A26E47F for ; Mon, 7 Jul 2014 13:43:23 -0700 (PDT) Received: by mail-wg0-f50.google.com with SMTP id x13so3940650wgg.33 for ; Mon, 07 Jul 2014 13:43:22 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140701195427.GA11155@nuc-i3427.alporthouse.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Chris Wilson , "Mateo Lozano, Oscar" , "Intel-gfx@lists.freedesktop.org" , "Madajczak, Tomasz" , "Rutkowski, Adam J" , "Jesse Barnes (jbarnes@virtuousgeek.org)" List-Id: intel-gfx@lists.freedesktop.org On Tue, Jul 01, 2014 at 08:54:27PM +0100, Chris Wilson wrote: > On Tue, Jul 01, 2014 at 05:16:30PM +0000, Mateo Lozano, Oscar wrote: > > > The issue is they need: > > > > > > A) A buffer object. > > > B) Bound to GGTT. > > > C) That userspace knows the GGTT offset of, so that they can program > > > OABUFFER with it. > > > D) That userspace can map so that they can read the reported counters. > > > > > > They used to create a bo, call bo_pin on it, use args->offset to program > > > OABUFFER (via MI_LOAD_REGISTER_IMM, I imagine), map it and read the > > > counter values. They cannot do this anymore. > > > > The answer might be that all of this needs to be done by the kernel > > itself, but then we need to provide an interface to userspace... > > Yes. If you need to pin a buffer for a register, then it needs to be > handled by the kernel. Especially one that provides information about > other users. Short-circuiting the entire discussion here. Afaik there's two OA modes: - inline with the batch with MI_REPORT_PERF - global with the ringbuffer setup with the OABUFFER registers The later should indeed be fully controlled by the kernel as Chris suggested and exposed as an off-cpu performance monitoring unit through the perf subsystem. Chris has rfc patches floating somewhere to do this for other gpu perf data. One fun thing here is the coordination between these two OA modes since iirc they both use the same setup registers for the performance counter configuration. No idea yet how to solve this. But really userspace shouldn't program ggtt offset, not even debug/performance measuring tools. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch